Physical Design Technical Lead

191 Altera Corporation; San Jose (CA); On-site; USD 209,500 - 299,200; Full time

Job summary

Altera in San Jose, CA is seeking a Physical Design Technical Lead to own complex SOC and block‑level implementation end‑to‑end. You will drive floorplanning, power integrity, synthesis, place‑and‑route, CTS and ECO closure, while mentoring a small team of engineers across multiple tape‑out projects.

The role emphasizes cross‑functional collaboration with RTL, DFT, packaging and analog teams, and advancing ML/AI‑driven optimization in production flows to achieve tight timing, power and area

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of progressive experience in physical design or SoC backend.
• 4+ years in a technical lead, senior lead, or principal-level role with ownership.
• At least 3 successful tape-outs with ownership at 7nm or below.
• 5+ years of SoC-level floorplanning, top-level integration, and full-chip implementation.
• 10+ years with Synopsys Fusion Compiler and/or Cadence Innovus.
• 8+ years of static timing analysis and closure with PrimeTime.
• 5+ years of power integrity analysis and sign-off with RedHawk or Voltus.
• 5+ years of multi-voltage and low-power design methodologies (UPF/CPF).
• 5+ years of physical verification and sign-off with Calibre DRC/LVS (PVS exposure).
• 8+ years scripting in Tcl; 3+ years in Python/Perl.
• 2+ years evaluating ML/AI-driven PD tools; translating outputs to design actions.
• 2+ years Python-based data pipelines for design metrics.

Responsibilities

• Own floorplan architecture and power domain partitioning for large SOCs.
• Drive block-level implementation through synthesis, placement, CTS, and ECO closure.
• Lead cross-functional convergence on timing, power, and area targets across tape-outs.
• Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges.
• Define and enforce physical design guidelines, constraints (SDC/UPF), and standards.
• Achieve signoff: STA, IR drop, electromigration, DRC/LVS, antenna.
• Drive PPA optimization: floorplanning, clock topology, routing resource planning.
• Lead critical-path analysis and timing-driven ECO resolution with teams.
• Manage hierarchy vs flat implementation flows and partitioning trade-offs.
• Champion ML/AI-based optimization in production PnR flows; integrate tools.
• Develop feedback loops between signoff results and ML training data pipelines.
• Present findings at design reviews and EDA forums; mentor 3–8 engineers.

Skills

Leadership

Mentoring

Tape-out experience

Scripting (Tcl/Python/Perl)

ML/AI PD knowledge

Education

Master’s degree in Electrical/Computer Engineering

Tools

Fusion Compiler

Innovus

Calibre DRC/LVS

PVS

PrimeTime

UPF/CPF

RedHawk

Voltus

Tcl scripting

Python scripting

Perl scripting

ML/AI PD tools

Job description

About Altera

Altera is the world’s largest pure‑play FPGA solutions provider, with four decades of FPGA expertise. Our mission is to deliver programmable technologies that help customers innovate and scale across AI, cloud, networking, automotive, and edge computing.

Role Overview

We are looking for a Physical Design Technical Lead to own complex SOC and block‑level implementation challenges end‑to‑end. The role encompasses floorplanning, power intent, synthesis, place‑and‑route, clock tree synthesis, ECO closure, and final sign‑off. It also involves shaping future ML/AI‑driven implementation flows and mentoring a small team of physical design engineers.

Key Responsibilities

• Own floorplan architecture and power domain partitioning for large, multi‑million‑instance SOC designs.
• Drive block‑level implementation through synthesis, place‑and‑route, CTS, and ECO closure with sign‑off quality results.
• Lead cross‑functional convergence on timing, power, and area targets across multiple concurrent tape‑out projects.
• Collaborate with RTL, DFT, packaging, and analog teams to resolve integration challenges proactively.
• Define and enforce physical design guidelines, constraint authoring (SDC/UPF), and methodology standards.
• Achieve full signoff closure: STA (multi‑corner, multi‑mode), IR drop, electromigration, DRC/LVS, antenna.
• Drive PPA optimization strategies, including innovative floorplanning, clock topology, and routing resource planning.
• Lead critical‑path analysis and timing‑driven ECO resolution with design and library teams.
• Manage hierarchy and partitioning trade‑offs for hierarchical versus flat implementation flows.
• Champion the integration of ML/AI‑based optimization engines into production PnR flows.
• EVALUATE and productize emerging AI tools from EDA vendors and internal research.
• Develop and maintain feedback loops between signoff results and ML training data pipelines.
• Partner with CAD and automation teams to deploy AI‑driven ECO, congestion prediction, and closure acceleration scripts.
• Present findings and flow enhancements at internal design reviews and external EDA forums.
• Mentor a team of 3–8 physical design engineers across multiple project tracks.
• Lead design reviews, closure reviews, and retrospectives to drive continuous improvement.
• Represent Physical Design in architecture planning meetings and influence design‑for‑implementability decisions.
• Contribute to internal white papers, methodology documentation, and IP reuse initiatives.

Qualifications

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of progressive experience in physical design or SoC backend for advanced semiconductor products.
• 4+ years in a technical lead, senior lead, or principal-level physical design role with ownership of complex physical design execution.
• At least 3 successful tape‑outs with direct hands‑on ownership at advanced process nodes (7nm or below).
• 5+ years of SoC‑level floorplanning, top‑level integration, and full‑chip physical implementation experience.
• 10+ years of hands‑on experience with Synopsys Fusion Compiler and/or Cadence Innovus.
• 8+ years of static timing analysis and closure using Synopsys PrimeTime (including MMMC, SI/crosstalk, and path‑based analysis).
• 5+ years of power integrity analysis and sign‑off using Ansys RedHawk or Cadence Voltus.
• 5+ years of multi‑voltage and low‑power design methodologies (UPF/CPF, MTCMOS, retention, isolation).
• 5+ years of physical verification and sign‑off flows using Mentor Calibre DRC/LVS, with exposure to Cadence PVS.
• 8+ years of scripting and automation in Tcl, and 3+ years in Python, Perl, or similar languages.
• 2+ years experience evaluating ML/AI‑driven physical design tools or methodologies.
• 2+ years experience applying custom ML/AI‑based workflows for timing prediction, hotspot detection, congestion modelling, or PPA optimization.
• 2+ years interpreting ML model outputs and translating them into actionable design decisions.
• 2+ years working with Python‑based data pipelines for design metric collection, analysis, or visualization.

Preferred Qualifications

• Experience with FPGA or structured‑ASIC fabric implementation.
• Knowledge of Altera‑specific implementation best practices.
• Exposure to 3DIC / chiplet integration (UCIe, EMIB, hybrid bonding constraints).
• High‑speed I/O integration experience (PCIe Gen 5/6, HBM PHY, SerDes) within SOC physical implementation.
• Contributions to EDA vendor beta programs, academic publications, or conference presentations.
• Experience with formal verification handoff flows and CDC/RDC methodology integration.
• Familiarity with advanced sign‑off (path‑delay rules, SI‑aware fixing, node‑specific design rule awareness).
• Prior experience at semiconductor IP companies, EDA vendors, or top‑tier fabless design houses.

Job Details

Salary Range: $209,500 – 299,200 USD (Bay Area California). Bonus and incentive opportunities may apply.

Job Type: Regular

Shift: Shift 1 (United States of America)

Primary Location: San Jose, California, United States

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Additional Information

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

```,