Senior Physical Design Engineer (Remote) — ASIC P&R Expert

BTA Design Services; California (MO); Hybrid; USD 120,000 - 190,000; Full time

Benefits offered by this job

Fully remote

Job summary

BTA Design Services is seeking a Senior Physical Design Engineer for a fully remote role. You will own backend implementation from netlist to GDSII on challenging blocks, using advanced flows on FinFET nodes.

Collaborate with a strong team to deliver production-ready ASICs and align with RTL/DFT teams. Applicants should bring 8+ years in ASIC P&R, hands-on EDA proficiency (Synopsys, Cadence), and strong scripting.

Qualifications

• 8+ years of experience in ASIC digital place and route.
• Hands-on experience with leading EDA tools (Synopsys, Cadence).
• Strong understanding of FinFET nodes, DRC and P&R requirements.
• Experience with floorplanning.
• Solid grasp of CTS and clock timing.
• Knowledge of IR-drop optimization strategies.
• Experience with timing closure and ECO implementation (PT-ECO/Tweaker).
• Strong scripting skills.
• Exposure to synthesis, StarRC, PT DMSA, RedHawk, Calibre, and formal verification.

Responsibilities

• Run place and route flows and analyze results.
• Create floorplans to support synthesis.
• Drive timing closure and perform physical verification.
• Debug tool-related, timing, DFT, and design issues.
• Collaborate with RTL/design teams to improve implementation friendliness.
• Apply timing ECOs as needed.
• Run timing reports with PrimeTime.
• Develop power/area optimization strategies.
• Perform IR-drop analysis and optimize it.
• Coordinate with analog/front-end teams on objectives.

Skills

ASIC design

Place & Route

Floorplanning

CTS/Clock design

IR-drop optimization

Timing closure

ECO implementation

Scripting

RTL collaboration

Tools

Synopsys

Cadence

PrimeTime

PT-ECO/Tweaker

StarRC

Calibre

DMSA

RedHawk

Job description

BTA Design Services is seeking a Senior Physical Design Engineer for a fully remote role. You will own backend implementation from netlist to GDSII on challenging blocks, using advanced flows on FinFET nodes.

Collaborate with a strong team to deliver production-ready ASICs and align with RTL/DFT teams. Applicants should bring 8+ years in ASIC P&R, hands-on EDA proficiency (Synopsys, Cadence), and strong scripting.