Senior Physical Design Engineer - Remote/Hybrid, TCL/Python

Quest Global; San Jose (CA); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Quest Global seeks an experienced physical design engineer to drive cutting-edge IP blocks for 2nm/3nm/5nm nodes in network switch products. You will craft floorplans, power plans, CTS and routing using Cadence Innovus and related tools.

You will write TCL scripts for custom/semi-custom standard cells placements and clock-tree adjustments, ensuring STA/IR/EM/LVS/DRC compliance and excellent timing margins. Collaboration with RTL/DFT teams is essential.

Qualifications

• MSEE/MSCS with 6+ years of experience.
• Expertise with Cadence Innovus/Atop physical design tools.
• Experience with Calibre LVS/DRC.
• Experience in low power and signal integrity.
• Collaborate with RTL & DFT teams.
• Strong TCL/Python scripting; Perl is a plus.
• Good debugging skills.

Responsibilities

• Perform physical design of 2nm/3nm/5nm multi-GHz IP for network switch products.
• Create floorplans, power plans, CTS, and routing using state-of-the-art EDA tools like Innovus.
• Write TCL scripts for custom/semi-custom standard cells placements and clock-tree adjustments/routing.
• Achieve design specs (STA/IR/EM/LVS/DRC) with strong timing analysis and CTS knowledge.

Skills

MSEE/MSCS

Innovus/Atop

Calibre LVS/DRC

Low Power SI

RTL & DFT collaboration

TCL/Python scripting

Education

MSEE/MSCS

Tools

Innovus

Atop

Calibre

Python

TCL scripting

Perl

Job description

Quest Global seeks an experienced physical design engineer to drive cutting-edge IP blocks for 2nm/3nm/5nm nodes in network switch products. You will craft floorplans, power plans, CTS and routing using Cadence Innovus and related tools.

You will write TCL scripts for custom/semi-custom standard cells placements and clock-tree adjustments, ensuring STA/IR/EM/LVS/DRC compliance and excellent timing margins. Collaboration with RTL/DFT teams is essential.