Lead Physical Design Engineer

Quest Global; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Quest Global offers engineering roles focused on advanced semiconductor physical design, delivering on 2nm/3nm/5nm projects with Cadence Innovus/Atop. You will work closely with RTL and DFT teams, use TCL scripting to automate placement and routing, and ensure critical checks like LVS/DRC, STA and power integrity are met.

We are seeking engineers with MSEE/MSCS (8+ years) or BSEE/BSCS (10+ years) and strong scripting skills in TCL/Python.

Qualifications

• MSEE/MSCS with 8+ years experience (BSEE/BSCS 10+ years)
• Expertise in Cadence Innovus/Atop physical design tools
• Experience with Calibre LVS/DRC
• Low power and signal integrity experience
• Work closely with RTL & DFT designers
• Strong TCL/Python scripting knowledge; Perl is a plus
• Good debugging skills and ability to work around issues

Responsibilities

• Perform physical design of 2nm/3nm/5nm using state-of-the-art EDA tools
• Create floorplans, powerplans, CTS and routing to meet specs
• Write TCL scripts to automate placements, clock tree adjustments, routing
• Collaborate with designers to ensure STA/IR/EM/LVS/DRC goals are met

Skills

TCL scripting

Python scripting

Debug skills

Strong RTL/DFT collaboration

Education

MSEE/MSCS

BSEE/BSCS

Tools

Cadence Innovus/Atop

Calibre LVS/DRC

Job description

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

Perform physical design of 2nm/3nm/5nm. Be able to come up with floorplan, powerplan, cts and routing of the design using state-of-art EDA tools like Innovus. Work closely with designers and must be able to write TCL script to perform custom/semi-custom standard cells placements/clock tree adjustments/routing to achieve design specs (STA/IR/EM/LVS/DRC). Good timing analysis and CTS knowledge is required.

• MSEE/MSCS + 8years (BSEE/BSCS 10+ years)
• Expertise in Cadence Innovus/Atop physical design tools
• Experience on Calibre LVS/DRC
• Low power, signal integrity experience
• Work closely with RTL & DFT designers
• Strong TCL/Python scripting knowledge required, Perl is a plus.
• Good debug skill and be able to work around issues