Physical Design Engineer – 3DIC

Value Innovation Labs Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Value Innovation Labs Inc. is seeking an experienced Physical Design Engineer to drive end-to-end ASIC/SoC implementation for advanced nodes. You will own the RTL-to-GDSII flow and collaborate with IP and foundry partners to deliver reliable, high-performance silicon.

The role emphasizes 3D-IC integration, power-aware design, and automated flows. You will lead timing closure (>1GHz), CTS, floorplanning, and sign-off activities while mentoring junior engineers in Tcl/Python/Perl scripting.

Qualifications

• 5+ to 10+ years in ASIC/SoC Physical Design with multiple full-cycle tape-outs.
• Solid understanding of MMCM, signal integrity, and 3D packaging technologies.
• Experience with industry-standard EDA tools (Cadence or Synopsys).
• Proficiency in scripting Tcl is mandatory; Python or Perl also valued.

Responsibilities

• Own RTL-to-GDSII flow including physical-aware synthesis, floorplanning, placement, routing, and CTS.
• Lead 3D-IC heterogenous integration and manage TSV planning, IR drop, EM, STA.
• Focus on low-power design using UPF/CPF with timing closure for >1GHz designs.
• Develop automation scripts in Tcl, Python, or Perl with IP/foundry partners.

Skills

ASIC/SoC PD

MMCM knowledge

Signal integrity

3D packaging

Tcl scripting

Python scripting

Perl scripting

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Synopsys PrimeTime

Job description

We are looking for an experienced Physical Design Engineer – 3DICto join the team.

What You Will Do:

Full-Stack Physical Design: Owning the RTL-to-GDSII flow, including physical-aware synthesis, floor planning, placement, routing, and clock tree synthesis (CTS).

3D-IC and Signoff Execution: Working on 3D heterogeneous integration and multi-die assemblies, managing TSV (Through-Silicon Via) planning, IR drop, electro-migration (EM), and static timing analysis (STA).

Power & Performance: Focusing on low-power implementation using UPF/CPF and strict timing closure for high-frequency designs (>1GHz).

Methodology Development: Collaborating with IP/foundry partners and developing automation scripts in Tcl, Python, or Perl.

What you will Bring:

Experience: 5+ to 10+ years of hands-on ASIC/SoC Physical Design experience with multiple full-cycle tape-outs at advanced nodes (5nm, 3nm, or 2nm).

Domain Expertise: Solid understanding of multi-corner multi-mode (MMCM), signal integrity, and 3D packaging technologies.

Tool Proficiency: Deep experience with industry-standard EDA tools like Cadence (Innovus, Tempus, Voltus) or Synopsys (ICC2, PrimeTime).

Scripting Skills: Proficiency in Tcl (mandatory), Python, or Perl