Senior Physical Design Engineer - High-Speed ASICs (5nm/3nm)

Lumilens; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Health insurance

Professional development

Cutting-edge technology access

Cloud platforms access

Collaborative work environment

Job summary

Lumilens is seeking a Senior Physical Design Engineer to join our silicon design team, developing high‑performance ASICs on 5nm and 3nm TSMC nodes. You will own physical implementation from RTL to GDSII and drive timing and power closure for ultra‑high‑speed designs.

Collaborate with RTL, STA, IP, and verification teams to solve advanced implementation challenges. Proficiency in floorplanning, placement, CTS, routing, and RC extraction is essential, along with scripting skills in Tcl or Python

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below.
• Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging.
• Hands-on experience with tools such as Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Siemens Calibre, along with scripting skills in Tcl, Python, or Perl.

Responsibilities

• Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes.
• Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip.
• Apply physical design techniques for multi‑voltage and multi‑frequency domains, hierarchical implementation, physical‑aware synthesis, congestion mitigation, skew optimization, and RC extraction‑aware placement and routing.
• Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry‑standard verification tools.

Skills

8+ years of physical design experience

Floorplanning

Placement

CTS

Routing

IR drop mitigation

Timing closure

Signoff debugging

Tcl scripting

Python scripting

Perl scripting

High‑Speed PHY implementation

Advanced-node signoff

2.5D/3D design experience

CoWoS or SoIC‑X knowledge

Education

Bachelor’s or Master’s degree in Electrical/Electronics Engineering or related field

Tools

Synopsys ICC2

Cadence Innovus

RedHawk SC

Voltus

Siemens Calibre

Job description

Lumilens is seeking a Senior Physical Design Engineer to join our silicon design team, developing high‑performance ASICs on 5nm and 3nm TSMC nodes. You will own physical implementation from RTL to GDSII and drive timing and power closure for ultra‑high‑speed designs.

Collaborate with RTL, STA, IP, and verification teams to solve advanced implementation challenges. Proficiency in floorplanning, placement, CTS, routing, and RC extraction is essential, along with scripting skills in Tcl or Python