Senior Physical Design Engineer - High-Freq SoC Expert

Quest Global; United States; On-site; USD 140,000 - 200,000; Full time

Job summary

Quest Global is seeking an experienced Physical Design Engineer in the United States to lead and execute SoC floor planning, place & route, and timing convergence for high-frequency designs. Strong expertise in power and clock distribution, geometry effects, and large SOCs (>100M gates) is required.

Collaboration across global teams and scripting skills in TCL/Python are essential. The ideal candidate holds a bachelor's degree in CS/CE or an equivalent field and has hands-on experience with top

Qualifications

• 8+ years of experience in physical design.
• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
• Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre
• Hands-on experience in SoC floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
• Knowledge of geometry/process/device technology implications on physical design
• Experience with large SOC designs (>100M gates) with frequencies over 1GHZ
• Experience collaborating effectively with both internal and external teams across various functions and geographic locations
• Programming/scripting skills: TCL, Python, Perl or Shell

Skills

SoC floor planning

Place & route

Timing convergence

Power distribution

Clock distribution

High-frequency design

Team collaboration

Scripting: TCL/Python

Large SOC (>100M gates)

Education

Bachelor's degree in CS/CE or equivalent

Tools

DC/Genus

Innovus/ICC2

Primetime

Redhawk/Voltus

Calibre

Job description

Quest Global is seeking an experienced Physical Design Engineer in the United States to lead and execute SoC floor planning, place & route, and timing convergence for high-frequency designs. Strong expertise in power and clock distribution, geometry effects, and large SOCs (>100M gates) is required.

Collaboration across global teams and scripting skills in TCL/Python are essential. The ideal candidate holds a bachelor's degree in CS/CE or an equivalent field and has hands-on experience with top