Application Engineer, Physical Design for Advanced Nodes

Synopsys Inc; Sunnyvale (CA); On-site; USD 190,000 - 240,000; Full time

Benefits offered by this job

Health benefits

Financial benefits

Job summary

Synopsys Inc. is seeking an experienced ASIC physical design engineer to partner with customers on challenging 7nm+ designs. You will tackle RTL-to-GDS flows, timing closure, and PPA improvements using Fusion Compiler or ICC2 to move designs forward.

You will work directly with customers, translate constraints into concrete plans, run benchmarks, and contribute to methodology development while collaborating with R&D, product management, and field teams. Travel to customer sites may be required.

Qualifications

• Experience with RTL-to-GDS flows and advanced node challenges.
• Hands-on timing closure, placement, and routing on 7nm+ processes.
• Proficiency with Synopsys backend tools and static timing analysis.

Responsibilities

• Support customer engagements on Synopsys physical design tools to hit PPA targets.
• Debug complex physical design issues across RTL-to-GDS flow including timing and power.
• Develop and deliver methodology recommendations for customer constraints and schedules.
• Run benchmarks and proofs-of-concept to showcase AI-driven optimization.
• Collaborate with R&D, product management, and field teams to translate pain points into requirements.
• Present technical content to customer teams and management, linking tool capabilities to outcomes.
• Travel to customer sites for onsite support, training, and design reviews.

Skills

RTL-to-GDS flows

Placement

Clock tree synthesis

Routing

Timing closure

AI-driven optimization

Static timing analysis

Communication skills

Electromigration awareness

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree (preferred)

Tools

Fusion Compiler

ICC2

Design Compiler

PrimeTime

Job description

Synopsys Inc. is seeking an experienced ASIC physical design engineer to partner with customers on challenging 7nm+ designs. You will tackle RTL-to-GDS flows, timing closure, and PPA improvements using Fusion Compiler or ICC2 to move designs forward.

You will work directly with customers, translate constraints into concrete plans, run benchmarks, and contribute to methodology development while collaborating with R&D, product management, and field teams. Travel to customer sites may be required.