Lead Physical Synthesis CAD Engineer for SoC Performance

Apple Inc.; United States; On-site; USD 240,000 - 340,000; Full time

Job summary

Apple Inc. is seeking a senior synthesis engineer to directly impact the performance and power efficiency of future iPhone, iPad, and Mac silicon.

You will own the synthesis challenges from RTL through GDS signoff and collaborate with design teams to define effective methodologies. You will develop techniques, scripts, and automated flows, validate full PNR/STA runs, and demonstrate tangible PPA improvements.

Qualifications

• Experience with TCL, Python or Perl scripting languages.
• Experience with industry standard Synthesis tools such as Fusion Compiler or Genus.
• Experience working with CAD Tools & flow.
• Minimum requirement of BS + 20 years of relevant industry experience.

Responsibilities

• Develop breakthrough physical synthesis techniques and validate them with full implementation flows (PNR, STA, power analysis).
• Apply advanced RTL optimization techniques to achieve substantial improvements in performance, power, and area (PPA).
• Partner with design teams to define optimal methodologies and flows, enabling them to achieve superior PPA results.
• Create custom tools and ML-based methodologies for today's most challenging high-performance, low-power design problems.
• Drive synthesis innovation that enables Apple's next-generation processor architectures.
• Influence EDA vendor tool development by solving the hardest problems.
• Deploy solutions across multiple critical Apple Silicon projects.

Skills

TCL

Python

Perl

Education

BS in Electrical Engineering or Computer Science

Tools

Fusion Compiler

Genus

CAD Tools & Flow

Job description

Apple Inc. is seeking a senior synthesis engineer to directly impact the performance and power efficiency of future iPhone, iPad, and Mac silicon.

You will own the synthesis challenges from RTL through GDS signoff and collaborate with design teams to define effective methodologies. You will develop techniques, scripts, and automated flows, validate full PNR/STA runs, and demonstrate tangible PPA improvements.