Senior Physical Design Engineer - High-Performance IP

Advanced Micro Devices, Inc.; Santa Clara (CA); In loco; USD 180.000 - 240.000; Tempo pieno

Descrizione del lavoro

AMD is seeking a collaborative Physical Design Engineer to drive RTL-to-GDS flows and deliver high-performance IP. You will lead timing-driven place and route, floorplanning, and signoff while coordinating with distributed teams to ensure quality, power, and timing targets are met.

This role emphasizes automation, design methodology, and scalable engineering processes. A degree in EE/CS is preferred; visa sponsorship is not available.

Competenze

• Experience taking digital designs through RTL-to-GDS physical design flow.
• Knowledge of high-speed SerDes PHY or high-performance IP designs is preferred.
• Experience with automated logic synthesis and timing-driven place and route for datapath and control logic.
• Familiarity with clock tree synthesis, power gating, and design optimization.

Mansioni

• Drive physical implementation of high-performance RTL blocks through synthesis, floorplanning, timing-driven place and route, and signoff.
• Develop and apply automated design flows for clock tree synthesis, clock and power gating, buffer/repeater insertion, and scan stitching.
• Analyze and optimize designs to meet timing, power, area, and electrical quality targets.
• Support floorplanning, design methodology development, and IP integration.
• Perform and support checks for timing, physical, and electrical quality; troubleshoot issues with design teams.
• Identify opportunities to improve automation, methodology and cycle time; support final signoff.

Conoscenze

RTL-to-GDS flow

High-speed SerDes PHY

Timing analysis

Power optimization

Automation flows

Formazione

Bachelor's or Master's in Electrical Engineering or Computer Science

Strumenti

Logic synthesis tools

Place & route tools

Physical verification tools

Timing analysis tools

Descrizione del lavoro

AMD is seeking a collaborative Physical Design Engineer to drive RTL-to-GDS flows and deliver high-performance IP. You will lead timing-driven place and route, floorplanning, and signoff while coordinating with distributed teams to ensure quality, power, and timing targets are met.

This role emphasizes automation, design methodology, and scalable engineering processes. A degree in EE/CS is preferred; visa sponsorship is not available.