Lead High-Speed SerDes Analog Layout Engineer

AMD; San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

AMD's SerDes Technology Group is seeking an experienced analog/mixed-signal layout design engineer with supervisory responsibilities to join our team in San Jose, CA. You will contribute to high-performance SerDes solutions enabling next-gen AMD CPU and GPU products, overseeing layout resources and driving productivity in a global, multi-time-zone environment.

The role requires a passion for high-speed layout design, strong analytical and communication skills, and collaboration with engineers

Qualifications

• Bachelor's degree in EE/CE or IC layout training with IC Layout working experience.
• Strong communication skills and teamwork.
• Experience in analog/mixed-signal layout is preferred.

Responsibilities

• Layout design of high speed SerDes analog mixed-signal circuits per specs.
• Block-level physical implementation including floorplanning and routing.
• Post-layout circuit performance analysis participation.
• Engage in block/IP/chip level integration activities.
• Estimate schedules and report progress.
• Contribute to layout methodology and flow development.
• Drive layout productivity through automation and pcells.
• Supervise onsite/offsite layout resources and address quality issues.

Skills

High speed layout design

Team player

Communication skills

Education

Bachelor degree in EE/CE or IC layout training

Tools

Cadence SKILL

Scripting (Perl, Python, Tcl)

Job description

AMD's SerDes Technology Group is seeking an experienced analog/mixed-signal layout design engineer with supervisory responsibilities to join our team in San Jose, CA. You will contribute to high-performance SerDes solutions enabling next-gen AMD CPU and GPU products, overseeing layout resources and driving productivity in a global, multi-time-zone environment.

The role requires a passion for high-speed layout design, strong analytical and communication skills, and collaboration with engineers