Physical Design Engineer

Infobahn Softworld Inc; California; On-site; USD 120,000 - 170,000; Full time

Job summary

Infobahn Softworld Inc is seeking a Physical Design Engineer to take RTL to GDS with synthesis, place-and-route, timing closure and physical verification.

You will work on high-speed SerDes PHY designs, automate design flows, clock tree synthesis, floor planning, IP integration and final sign-off for large IP deliveries.

Required: 2–5+ years in high-speed IP, Python/Perl, experience with P&R tools, RTL, and a degree in EE/CS; master’s preferred.

Qualifications

• 2–5+ years in high-speed SerDes PHY designs or other high-performance IP designs.
• Python and/or Perl proficiency; other languages a plus.
• Experience in automating design flows for RTL synthesis and timing-driven P&R (Verilog preferred).
• Experience in clock tree synthesis, clock/power gating techniques, buffer/repeater insertion, scan stitching, and design optimization.

Responsibilities

• Automate synthesis and timing-driven P&R of RTL blocks for high-speed datapath and control logic applications.
• Support floor planning, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Develop automated design flows for clock tree synthesis, clock and power gating, and design cycle time reduction.

Skills

RTL

Python/Perl

Automation

Place & Route

Timing Closure

Floor Planning

IP Integration

Sign-off

Education

Master’s degree in EE/CS or related field

Bachelor’s degree in EE/CS or related field

Tools

Synthesis tools

Place & Route tools

Timing analysis tools

Layout/Circuit simulation tools

Job description

This is a Physical Design Engineering role that will require to take the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification.

RESPONSIBILTIES:

This engineer will work on high-speed multi-gigabit SerDes PHY designs. This includes automated synthesis and timing driven place and route of RTL blocks for high speed Datapath and control logic applications, automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. You will also support floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.

PREFERRED SKILLED SETS:

• 2-5+ years working experience, preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs
• Proficiency in Python and/or Perl is required. Additional languages are a plus.
• Versatility with scripts to automate design flow, and quality checks.
• Experience in automated synthesis and timing driven place and route of RTL blocks (Verilog experience preferred) for high speed Datapath and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, buffer/repeater insertion, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction
• Strong background in digital circuit techniques, efficient and robust implementation topologies for logic functions, logic optimization, and transistor level circuit topologies for high speed, low power applications
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery.
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation

EDUCATION:

• Major in EE, CS or related, master’s degree preferably with high-speed multi-gigabit SerDes PHY designs or other high-performance IP designs.