Senior PD Methodology Engineer - Cloud ASICs

Annapurna Labs; Cupertino (CA); Presencial; USD 177.000 - 247.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health insurance

RSUs

401(k) matching

Paid time off

Parental leave

Descripción de la vacante

Annapurna Labs (U.S.) Inc. in Cupertino seeks a hardware design engineer to lead CAD flow development for ASIC physical design, optimizing for high performance and low power in data-center AI workloads.

You will collaborate with RTL, PD, and package teams, evaluate new EDA tools, and drive scalable design methodologies across cloud-scale ML acceleration platforms. The role offers opportunity to impact cost, performance, and QoR in large-scale deployments.

Formación

• Bachelor's degree in Electrical Engineering or related field.
• 3+ years in developing design methodology or CAD flows for advanced technology nodes.
• Experience scripting for implementation and sign-off tools in TCL, Perl, and/or Python.
• Solid understanding of ASIC physical design and methodologies (synthesis, PnR, STA, formal verification).
• Proven track record delivering metric-driven PPA flow development and support.

Responsabilidades

• Create and support innovative physical design methodology and CAD flows.
• Develop cloud infrastructure to support physical design work.
• Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement.
• Create dashboards/reports for project tracking and QoR/stats visualization.
• Interface with RTL, PD, Package Design, DFT and other teams to improve methodologies and efficiencies.
• Work with EDA tool vendors to evaluate new tools and resolve bugs.

Conocimientos

CAD flow development

PPA flow

ASIC physical design

RTL2GDS knowledge

Educación

Bachelor's degree in Electrical Engineering or related field

Herramientas

TCL

Perl

Python

Innovus

ICC2

FusionCompiler

STA

Sign-Off

Descripción del empleo

Annapurna Labs (U.S.) Inc. in Cupertino seeks a hardware design engineer to lead CAD flow development for ASIC physical design, optimizing for high performance and low power in data-center AI workloads.

You will collaborate with RTL, PD, and package teams, evaluate new EDA tools, and drive scalable design methodologies across cloud-scale ML acceleration platforms. The role offers opportunity to impact cost, performance, and QoR in large-scale deployments.