Senior PD Engineering Manager – AI Accelerator SoCs

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 240,000 - 324,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

RSUs and paid time off

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino seeks a Senior Manager, Physical Design Engineering to build and lead a world-class PD team for multi‑billion‑transistor ML accelerator SoCs on latest tech nodes.

You will own the PD strategy for Inferentia, Trainium, and future products, drive PPA improvements, and collaborate with RTL, DFT, STA, Packaging, and Validation teams to ensure successful tapeouts.

Qualifications

• 5+ years leading PD teams of 8+ engineers.
• 10+ years hands-on ASIC/SoC PD across multiple advanced nodes (7nm/5nm/3nm).
• Technical depth from RTL to GDSII: floorplanning, CTS, routing, timing closure, PDN, signoff.
• Mastery of Synopsys and Cadence toolchains; Calibre for DRC/LVS.
• Deep expertise in STA and power integrity (IR-drop, DVFS).
• Experience with high-speed PD (GHz datapaths, SerDes, DDR5, PCIe Gen5+).
• Hierarchical methodologies for very large SoCs (>1B transistors).
• Scripting proficiency in TCL, Python, Perl.

Responsibilities

• Build and lead a PD team of 10–15 engineers; headcount planning and performance reviews.
• Own PD strategy and roadmap for Inferentia, Trainium, and future products.
• Improve PPA via benchmarking, regression tracking, and dashboards.
• Provide hands-on leadership for timing closure, PDN architecture, and 2.5D/3D integration.
• Lead node enablement for 2nm or beyond with PDK evaluation and flow development.
• Define RTL-to-GDS2GDS methodologies; drive AI/ML-augmented design automation.
• Coordinate with foundry partners and EDA vendors on tool roadmap and optimization.
• Own tapeout execution, reviews, submittals, and post-silicon yield learning.

Skills

People management

ASIC/SoC PD

RTL-to-GDSII

Scripting (TCL/Python/Perl)

GHz PD timing

2.5D/3D integration

Tapeout leadership

Cross‑functional leadership

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus/Tempus

Siemens Calibre

Job description

Annapurna Labs (U.S.) Inc. in Cupertino seeks a Senior Manager, Physical Design Engineering to build and lead a world-class PD team for multi‑billion‑transistor ML accelerator SoCs on latest tech nodes.

You will own the PD strategy for Inferentia, Trainium, and future products, drive PPA improvements, and collaborate with RTL, DFT, STA, Packaging, and Validation teams to ensure successful tapeouts.