PD Methodology Engineer II - Cloud-Scale ASIC Design

Annapurna Labs; San Diego (CA); In loco; USD 177.000 - 247.000; Tempo pieno

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Cupertino, CA is hiring a design methodology and CAD flows engineer to advance cloud-scale ML acceleration hardware. You will optimize RTL-to-GDS flows, drive PPA improvements, and collaborate with RTL, Physical Design, and EDA teams to deliver high-performance, cost-effective devices.

The role requires 3+ years in design methodology, strong scripting skills, and a solid ASIC design background; experience with Innovus, ICC2, FusionCompiler, and Sign-Off is preferred.

Competenze

• Bachelor's degree in Electrical Engineering or related field.
• 3+ years in developing design methodology or CAD flows for advanced technology nodes.
• Experience writing production scripts for implementation and sign-off tools in TCL, Perl, Python.
• Solid understanding of ASIC physical design, flows, and methodologies including synthesis, PnR, STA, and formal verification.
• Proven track record of metric-driven PPA flow development and support.

Mansioni

• Create and support innovative physical design methodology and CAD flows.
• Develop cloud infrastructure to support physical design work.
• Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement.
• Create Dashboard/central reports for project tracking and visualizing QoR/stats
• Interface with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies.
• Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability.

Conoscenze

CAD flow development

Scripting TCL/Perl/Python

ASIC physical design

PPA flow development

Formazione

Bachelor's degree in Electrical Engineering or related field

Strumenti

Innovus

ICC2

FusionCompiler

STA

Sign-Off

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Cupertino, CA is hiring a design methodology and CAD flows engineer to advance cloud-scale ML acceleration hardware. You will optimize RTL-to-GDS flows, drive PPA improvements, and collaborate with RTL, Physical Design, and EDA teams to deliver high-performance, cost-effective devices.

The role requires 3+ years in design methodology, strong scripting skills, and a solid ASIC design background; experience with Innovus, ICC2, FusionCompiler, and Sign-Off is preferred.