Senior PCIe Subsystem RTL Architect

TYLsemi; San Jose (CA); Remote; USD 238,000 - 286,000; Full time

Benefits offered by this job

Stock options

Remote-friendly, global team

Job summary

TYLsemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for high‑performance compute chiplets.

You will drive integration of PCIe IP, define lane configurations, and oversee TL pipelines, VC and flow‑control, while collaborating with firmware and physical design teams. You will mentor RTL engineers, define verification plans with DV teams, and engage with customers on interface bring‑up.

Qualifications

• Bachelor’s/Master’s degree in electrical or computer engineering or equivalent.
• Extensive PCIe knowledge across TL, DL, PL and TLP handling.
• Experience integrating PCIe hard IP in production SoCs.

Responsibilities

• Own PCIe sub-system microarchitecture from PHY to Transaction Layer.
• Lead integration of third‑party PCIe IP and wrapper RTL.
• Define bifurcation, lane configuration, and mode management.
• Drive TL pipeline, TLP reception, routing and handoff.
• Own VC and flow-control architecture with fair arbitration.

Skills

PCIe architecture

Digital IC design

RTL design leadership

SystemVerilog

Multi-clock-domain design

SR‑IOV knowledge

UVM verification planning

Mentoring

CXL protocol knowledge

Education

BS/MS in Electrical/Computer Engineering or equivalent

Tools

Verilog/SystemVerilog

UVM

Job description

TYLsemi, Inc. is seeking a Principal PCIe Sub-system Front-end RTL lead to own the PCIe microarchitecture for high‑performance compute chiplets.

You will drive integration of PCIe IP, define lane configurations, and oversee TL pipelines, VC and flow‑control, while collaborating with firmware and physical design teams. You will mentor RTL engineers, define verification plans with DV teams, and engage with customers on interface bring‑up.