Principal PCIe Subsytem RTL Lead

MRL Consulting Group; California; Presencial; USD 180.000 - 260.000; Jornada completa

Descripción de la vacante

MRL Consulting Group is seeking a Principal PCIe Sub-system Front-end RTL Lead to drive development of next-generation chiplet-based SoCs for high-performance compute and AI applications. You will own the PCIe microarchitecture and lead RTL integration across PHY, MAC, and Transaction Layer.

Collaborate with firmware for register maps and telemetry, guide RTL engineers, and ensure timing closure with Physical Design while driving the PCIe verification strategy with DV teams.

Responsabilidades

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL, mode selection, telemetry hooks, and bridging logic to the chiplet’s internal fabric.
• Define and implement bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across operating modes.
• Specify and drive implementation of the Transaction Layer pipeline, including TLP reception, integrity checking, header classification, routing decisions, and downstream handoff.
• Own the Virtual Channel and flow-control architecture, including arbitration, traffic prioritization, and back-pressure handling.
• Define subsystem integration interfaces, including TLP-to-flit adaptation, flow-control mapping, and error handling at the subsystem boundary.
• Collaborate with firmware teams to define the PCIe register map, mode-selection interfaces, and runtime telemetry structures exposed to the on-chip management processor.
• Work with Physical Design to achieve timing closure across the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
• Own the PCIe performance budget for each operating mode, including bandwidth efficiency, Transaction Layer latency, and error-recovery overhead.
• Define the PCIe power-management architecture, including link-state transitions, ASPM policy, and integration with chiplet-level power-management schemes.
• Lead PCIe silicon bring-up planning, including bring-up sequences, debug instrumentation, loopback modes, and production-readiness criteria.
• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural direction and conducting RTL reviews.
• Partner with the DV team to define the PCIe UVM verification strategy, coverage model, and protocol-checker requirements.
• Serve as the technical point of contact for PCIe-related integration and interoperability questions.
• Author and maintain the PCIe subsystem microarchitecture specification throughout RTL implementation, verification, and sign-off.

Conocimientos

PCIe Sub-system

RTL Design

UVM Verification

Team Leadership

Descripción del empleo

We are looking for a Principal PCIe Sub-system Front-end RTL Lead to drive the development of next-generation chiplet-based SoCs for high-performance compute and AI applications.

What You’ll Do

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining block boundaries, data paths, and control interfaces.

• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL, mode selection, telemetry hooks, and bridging logic to the chiplet’s internal fabric.

• Define and implement bifurcation and lane-configuration logic, ensuring all supported lane-width configurations operate correctly across operating modes.

• Specify and drive implementation of the Transaction Layer pipeline, including TLP reception, integrity checking, header classification, routing decisions, and downstream handoff.

• Own the Virtual Channel and flow-control architecture, including arbitration, traffic prioritization, and back-pressure handling.

• Define subsystem integration interfaces, including TLP-to-flit adaptation, flow-control mapping, and error handling at the subsystem boundary.

• Collaborate with firmware teams to define the PCIe register map, mode-selection interfaces, and runtime telemetry structures exposed to the on-chip management processor.

• Work with Physical Design to achieve timing closure across the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.

• Own the PCIe performance budget for each operating mode, including bandwidth efficiency, Transaction Layer latency, and error-recovery overhead.

• Define the PCIe power-management architecture, including link-state transitions, ASPM policy, and integration with chiplet-level power-management schemes.

• Lead PCIe silicon bring-up planning, including bring-up sequences, debug instrumentation, loopback modes, and production-readiness criteria.

• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural direction and conducting RTL reviews.

• Partner with the DV team to define the PCIe UVM verification strategy, coverage model, and protocol-checker requirements.

• Serve as the technical point of contact for PCIe-related integration and interoperability questions.

• Author and maintain the PCIe subsystem microarchitecture specification throughout RTL implementation, verification, and sign-off.