Senior PCIe Subsystem RTL Architect

TylSemi, Inc.; San Jose (CA); Hybrid; USD 238.000 - 286.000; Vollzeit

Benefits dieser Stelle

Equity compensation

Zusammenfassung

TylSemi, Inc. in San Jose, CA seeks a Principal PCIe Subsystem RTL lead to own the PCIe microarchitecture from PHY to MAC and TL. You will lead integration of third-party PCIe IP, define lane configurations, and drive the TL pipeline across multiple operating modes.

The role requires deep PCIe expertise, SystemVerilog RTL skills, and experience with chiplet-based designs. Join a fast-paced team delivering scalable PCIe infrastructure for AI/HP systems.

Qualifikationen

• 10+ years of digital IC design experience with PCIe subsystem focus.
• Deep expertise in PCIe architecture: TL, DL, PL, TLPs, flow control, VCs, and error handling.
• Experience integrating PCIe hard IP into production SoC or chiplet designs.
• Background with SR-IOV, multi-function config, or hardware driver interfaces.
• Strong SystemVerilog RTL skills for complex state machines, FIFOs, arbiters, and controls.

Aufgaben

• Own PCIe subsystem microarchitecture from PHY to MAC and TL.
• Lead integration of third-party PCIe controller/PHY IP including wrapper RTL.
• Define lane configurations and ensure correct operation across modes.
• Drive TL pipeline, TLP reception, header classification, routing, handoff.

Kenntnisse

PCIe architecture

SystemVerilog RTL

RTL design

Multi-clock-domain design

SR-IOV

CXL protocol

Ausbildung

BS/MS in Electrical Engineering / Computer Engineering

Tools

SystemVerilog

UVM

PCIe IP integration

Wrapper RTL

Jobbeschreibung

TylSemi, Inc. in San Jose, CA seeks a Principal PCIe Subsystem RTL lead to own the PCIe microarchitecture from PHY to MAC and TL. You will lead integration of third-party PCIe IP, define lane configurations, and drive the TL pipeline across multiple operating modes.

The role requires deep PCIe expertise, SystemVerilog RTL skills, and experience with chiplet-based designs. Join a fast-paced team delivering scalable PCIe infrastructure for AI/HP systems.