Senior PCIe IP Design Lead (RTL/SystemVerilog)

Rambus; Hillsboro (OR); Hybrid; USD 108,000 - 201,000; Full time

Benefits offered by this job

Base salary

Bonus

Equity

401(k) match

Employee stock purchase plan

Medical and dental benefits

Time-off program

Gym membership

Job summary

Rambus in the United States is seeking a motivated Principal Design Engineer to join the PCIe IP design team. You will contribute to architecture and micro-architecture and implement designs in SystemVerilog, collaborating with an international team.

The role involves prototyping IPs on cutting-edge FPGAs, supporting existing IP generations, and working in a hybrid environment with three onsite days per week. A strong RTL background and Masters/PhD are preferred.

Qualifications

• RTL coding: Verilog / SystemVerilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
• 8+ years of experience with RTL Design.
• Good English skills, communication skills, and willingness to work with an international team.

Responsibilities

• Contribute to the architecture and micro-architecture of next generation PCIe IP.
• Implement these designs in System Verilog.
• Collaborate with the verification team to verify the IPs.
• Participate in prototyping of the IPs in cutting edge FPGAs.
• Contribute to support of existing generations of the IPs.

Skills

Verilog/SystemVerilog

RTL Design

English communication

PCIe knowledge

Education

Master's or PhD in Electrical/Computer Engineering

Tools

SystemVerilog

Verilog

Job description

Rambus in the United States is seeking a motivated Principal Design Engineer to join the PCIe IP design team. You will contribute to architecture and micro-architecture and implement designs in SystemVerilog, collaborating with an international team.

The role involves prototyping IPs on cutting-edge FPGAs, supporting existing IP generations, and working in a hybrid environment with three onsite days per week. A strong RTL background and Masters/PhD are preferred.