Principal PCIe Subsystem RTL lead

TYLsemi; United States; Remote; USD 180,000 - 320,000; Full time

Job summary

TYLsemi is seeking a Principal PCIe Sub-system Front-end RTL lead to drive the PCIe microarchitecture for next-gen chiplet-based SoCs. You will own from PHY to Transaction Layer, coordinating wrapper RTL, telemetry, and integration with the chiplet fabric.

You will mentor RTL engineers, collaborate on UVM verification, and work with the engineering team to meet timing and power-management goals for high-performance compute and AI silicon.

Qualifications

• 10+ years of digital IC design experience with PCIe subsystems.
• Deep expertise in PCIe architecture: TL, DL, PL, TLP, flow control and VC.
• Hands-on experience integrating PCIe hard IP and wrapper RTL.
• Background in SR-IOV or multi-function device configurations.
• Strong SystemVerilog RTL skills for production-grade pipelines and arbiters.
• Familiarity with CXL protocol knowledge and PCIe timing requirements.
• Experience with PCIe compliance testing and PCI-SIG processes.
• Knowledge of PCIe power management (L0s/L1, ASPM) and clock-domain issues.

Responsibilities

• Own the PCIe subsystem microarchitecture from PHY to TL and interface boundaries.
• Lead integration of PCIe hard IP, including wrapper RTL and telemetry hooks.
• Define lane configurations, data paths, and control interfaces for all modes.
• Drive TL pipeline design: TLP reception, headers, routing, and handoff.
• Manage Virtual Channel and flow-control architecture, with fair arbitration.
• Define PCIe interface to UVM verification and DV plans.
• Collaborate with management firmware for register map and telemetry.
• Work with PD lead to meet timing, resets, and floorplan constraints.
• Lead silicon bring-up planning and production readiness criteria.

Skills

PCIe architecture

Transaction Layer

Data Link Layer

Physical Layer

SystemVerilog RTL

RTL design and verification

Multi-clock-domain design

SR-IOV & multi-function device

PCIe power management

CXL protocol knowledge

PCIe compliance testing

UCIe / die-to-die bridging (desirable)

Education

BS/MS in Electrical/Computer Engineering or equivalent

Tools

UVM

Job description

We are looking for a Principal PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon .

WhatYou’llDo

• Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces.
• Lead the integration of third-party PCIe controller and PHY hard IP, including wrapper RTL that adds modeselection, telemetry hooks, and bridging logic to the chiplet’s internal fabric.
• Define and implement the bifurcation andlane-configurationlogic, ensuring all supported lane-width configurationsoperatecorrectly across the full range of operating modes.
• Specify and drive implementation of the Transaction Layer pipeline: TLP reception, integrity checking, header classification, routing decisions, and handoff to downstream subsystems.
• Own the Virtual Channel and flow-control architecture, ensuring fair arbitration andback-pressurehandling across all traffic classes.
• Define the integration interface to the PCIe subsystem such asTLP-to-flit adaptation, flow-control mapping, and error handling at the boundary.
• Collaborate with the management firmware team to define the PCIe register map, mode-select interface, and run-time telemetry structures exposed to the on-chip management processor.
• Work with the Physical DesignLeadto meet timing closure requirements for the PCIe subsystem, including MAC-PHY interface timing, reset sequencing, and floorplan constraints.
• Hold the PCIe performance budget for each operating mode: bandwidth efficiency, latency through the Transaction Layer, and error recovery overhead.
• Define the PCIe power management architecture — link state transitions, ASPM policy, and integration with the chiplet-level power coordination scheme.
• Lead PCIe silicon bring-up planning: definebringupsequence, debug instrumentation requirements, loopback modes, and the hand-off criteria for production readiness.
• Mentor and guide RTL design engineers responsible for PCIe subsystem implementation, providing architectural guidance and RTL review.
• Partner with the DV team to define the PCIe UVM verification plan, coverage model, andprotocol-checkerrequirements.
• Serve as the technical point of contact for PCIe-related customer integration questions, supporting anchor customer engagements on interface bring-up and interoperability.
• Author andmaintainthe PCIe subsystem micro-architecture specification, keeping it current through RTL implementation and sign-off.

What We’re Looking For

• 10+ years of digital IC design experience, with at least 4 years focused on PCIe subsystem design or integration at the block-lead or module-owner level.
• Deepexpertisein PCIe architecture: Transaction Layer, Data Link Layer, Physical Layer, TLP structure, flow control, Virtual Channels, and error handling.
• Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, andPnRconstraints.
• Background in SR-IOV, multi-function device configuration, or host software driver interaction at the hardware level.
• StrongSystemVerilogRTL skills: able to write, review, and own production RTL for complex pipelined state machines, FIFOs, arbiters, and control logic.
• CXL 1.1/2.0 or 3.0 protocol knowledge, particularly CXL.io andCXL.memtransaction handling built on the PCIe fabric.
• Solid understanding of PCIe PHY-MAC interface protocols and timing requirements,
• Experience with PCIe compliance testing and PCI-SIG certification process — understanding of test requirements, common failure modes, and debugmethodology.
• Familiarity with PCIe power management, L0s/L1 state machines, state transitions etc.
• Competency in multi-clock-domain design: async FIFO, CDC synchronizers, and clock crossing at the PCIe-to-internal-fabric boundary.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good To Have

• Experience with UCIe or another die-to-die protocol at the PCIe TLP adaptation layer — mapping TLPs to a flit-based D2D transport.
• Prior experience with protocol bridging or gearbox designs that span multiple PCIe generations.
• Familiaritywith PCIeIP integration, including customization and support engagement.
• Experience at an advanced-node (7 nm or below) tape-out, particularly with the timing closure and floorplan considerations for designs.

Compensation

The compensation range shown below represents total target cash compensation and includes both base salary and target bonus. Actual compensation will vary based on factors such as experience, skills, qualifications, job level, and work location.

In addition to cash compensation, this position is eligible for equity in the form of stock options, giving you the opportunity to share in the Company’s long-term growth and success.