Senior PCIe Subsystem RTL Lead for AI/HP SoCs

TYLsemi; United States; Remote; USD 180,000 - 320,000; Full time

Job summary

TYLsemi is seeking a Principal PCIe Sub-system Front-end RTL lead to drive the PCIe microarchitecture for next-gen chiplet-based SoCs. You will own from PHY to Transaction Layer, coordinating wrapper RTL, telemetry, and integration with the chiplet fabric.

You will mentor RTL engineers, collaborate on UVM verification, and work with the engineering team to meet timing and power-management goals for high-performance compute and AI silicon.

Qualifications

• 10+ years of digital IC design experience with PCIe subsystems.
• Deep expertise in PCIe architecture: TL, DL, PL, TLP, flow control and VC.
• Hands-on experience integrating PCIe hard IP and wrapper RTL.
• Background in SR-IOV or multi-function device configurations.
• Strong SystemVerilog RTL skills for production-grade pipelines and arbiters.
• Familiarity with CXL protocol knowledge and PCIe timing requirements.
• Experience with PCIe compliance testing and PCI-SIG processes.
• Knowledge of PCIe power management (L0s/L1, ASPM) and clock-domain issues.

Responsibilities

• Own the PCIe subsystem microarchitecture from PHY to TL and interface boundaries.
• Lead integration of PCIe hard IP, including wrapper RTL and telemetry hooks.
• Define lane configurations, data paths, and control interfaces for all modes.
• Drive TL pipeline design: TLP reception, headers, routing, and handoff.
• Manage Virtual Channel and flow-control architecture, with fair arbitration.
• Define PCIe interface to UVM verification and DV plans.
• Collaborate with management firmware for register map and telemetry.
• Work with PD lead to meet timing, resets, and floorplan constraints.
• Lead silicon bring-up planning and production readiness criteria.

Skills

PCIe architecture

Transaction Layer

Data Link Layer

Physical Layer

SystemVerilog RTL

RTL design and verification

Multi-clock-domain design

SR-IOV & multi-function device

PCIe power management

CXL protocol knowledge

PCIe compliance testing

UCIe / die-to-die bridging (desirable)

Education

BS/MS in Electrical/Computer Engineering or equivalent

Tools

UVM

Job description

TYLsemi is seeking a Principal PCIe Sub-system Front-end RTL lead to drive the PCIe microarchitecture for next-gen chiplet-based SoCs. You will own from PHY to Transaction Layer, coordinating wrapper RTL, telemetry, and integration with the chiplet fabric.

You will mentor RTL engineers, collaborate on UVM verification, and work with the engineering team to meet timing and power-management goals for high-performance compute and AI silicon.