Lead Chiplet Performance & Power Architect

TYLsemi; San Jose (CA); Remote; USD 204,000 - 250,000; Full time

Job summary

TYLsemi, Inc. is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization for chiplet integration including PCIe, UCIe, and NoC IPs.

You will own trade-off analyses that determine what gets taped out and work with ESL tools to model full-chiplet behavior. Qualifications include 6+ years in computer architecture, hands-on ESL tool experience, and strong Python and SystemC skills.

Qualifications

• BS/MS in Electrical Engineering or related field with 6+ years in computer architecture or performance modeling.
• Hands-on experience with ESL tools such as Platform Architect or Virtualizer.
• Strong knowledge of PCIe, UCIe, or AMBA NoC protocols; willing to learn others.
• Python scripting for automating large-scale simulations.
• Familiarity with SystemC and transaction-level modeling.

Responsibilities

• Own PPA exploration and tape-out trade-offs.
• Build TLMs using ESL suites to integrate IPs into a full-chiplet model.
• Define and validate hardware configuration parameters to maximize throughput.
• Characterize NoC/UCIe traffic to find congestion points.
• Collaborate with IP vendors to debug models and land new IP.

Skills

PPA optimization

System-level modeling

Python scripting

SystemC modeling

ESL tools

Traffic generators

IP integration

Education

BS in Electrical Engineering

MS in Electrical Engineering

Tools

Platform Architect

Virtualizer

SystemC

Job description

TYLsemi, Inc. is seeking a Lead Performance Architect to drive architectural configuration, system-level simulation, and PPA optimization for chiplet integration including PCIe, UCIe, and NoC IPs.

You will own trade-off analyses that determine what gets taped out and work with ESL tools to model full-chiplet behavior. Qualifications include 6+ years in computer architecture, hands-on ESL tool experience, and strong Python and SystemC skills.