Package Engineer

Entrada Ventures; Palo Alto (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity

Benefits

401k

Job summary

Entrada Ventures seeks a Senior Packaging Engineer in the Silicon Valley area to architect and deliver advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.

The candidate will define stack‑ups, engage with fabrication partners, and collaborate with IC design teams to ensure system‑level alignment and reliability across next‑generation products.

Qualifications

• B.S./M.S. in Electrical Engineering or related field.

Responsibilities

• Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO).
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
• Define substrate stack‑ups, bump pitch, ball pitch, routing, via structures, and material choices.
• Perform high‑speed signal escaping, routing and power distribution network design.
• Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
• Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system‑level needs.
• Evaluate emerging packaging technologies and drive adoption for next‑generation products.
• Support package‑level bring‑up, failure analysis, debug and qualification.

Skills

Multi‑die package design

UCIe integration

Substrate materials understanding

SI/PI concepts

Packaging subcontractors management

Interface with TSMC/OSAT

Package modeling tools

Education

B.S./M.S. in Electrical Engineering

Tools

HFSS

Sigrity

Job description

Who We Are

We are a stealth‑mode startup building foundational technology to address performance, scalability, and resiliency challenges in large‑scale AI data center clusters. We are backed by top‑tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on‑site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

Some Recent Press:

https://www.eetimes.com/startup-boosts-scale-up-to-1000-gpus-in-a-single-domain/

What We Need

A Senior Packaging Engineer responsible for architecting and delivering advanced multi‑die IC packages for high‑performance AI accelerators. This role focuses on package architecture, substrate design, manufacturability, and vendor engagement.

Key Responsibilities

• Select and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
• Define substrate stack‑ups, bump pitch, ball pitch, routing, via structures, and material choices for performance and manufacturability.
• Perform high-speed signal escaping, routing and power distribution network design.
• Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
• Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system‑level needs.
• Evaluate emerging packaging technologies and drive adoption for next‑generation products.
• Support package‑level bring‑up, failure analysis, debug and qualification.

Required Skills & Qualifications

• B.S./M.S. in Electrical Engineering or related field.
• Experience with multi‑die package design and UCIe (AP/SP) integration.
• Understanding of substrate materials, stack‑ups, and mechanical constraints.
• Familiarity with SI/PI concepts to collaborate effectively with electrical teams.
• Experience managing packaging subcontractors.
• Experience interfacing with TSMC/OSAT for bumping and packaging options.
• Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus.

Compensation

Target base salary for this role is $180,000–$240,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.

We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.

#LI-EW1