Senior Packaging Engineer — Bumping, RDL & 2.5D/3DIC Expert

Qualcomm; San Diego (CA); On-site; USD 192,000 - 288,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego seeks a Process Package Integration engineer focused on wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon nodes, foundries, bumping lines and OSATs.

You will define bumping flows, establish process windows, lead DOE-based optimization, and collaborate with suppliers to improve yield, reliability, and cost. The role requires strong cross-functional collaboration and hands-on leadership in a

Qualifications

• 8–10 years in silicon interconnect, bumping, or RDL process with NPI/QC experience.
• Experience with process-structure interaction in advanced packaging.
• Proven track record in production release and qualification for high-volume manufacturing.

Responsibilities

• Define bumping process flows and control plans for multiple nodes.
• Lead DOE-driven optimization, yield, and reliability improvements.
• Coordinate with foundries, bumping houses, and internal teams for capacity expansion.

Skills

Bumping process integration

Passivation/UBM/RDL/bump

Flip-chip bump design

Wafer-level packaging (RDL)

DOE design and analysis

Statistical data analysis

GR&R and SPC

NPI and high-volume production

Line qualification and ramp

Supplier management

Cross-functional collaboration

Interfacing with foundries/OSATs

Education

Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field

Tools

Calibre

Virtuoso

CAD

SiP

GDS

Job description

Qualcomm Technologies, Inc. in San Diego seeks a Process Package Integration engineer focused on wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon nodes, foundries, bumping lines and OSATs.

You will define bumping flows, establish process windows, lead DOE-based optimization, and collaborate with suppliers to improve yield, reliability, and cost. The role requires strong cross-functional collaboration and hands-on leadership in a