Sr. Staff Packaging Engineer- Process Package Integrity & Bumping

QUALCOMM, Inc.; San Diego (CA); On-site; USD 192,000 - 288,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an accomplished engineer to own wafer bumping process integration, qualification, and high-volume readiness across multiple silicon nodes.

You will drive DOE-based optimization, partner with foundries and OSATs, and lead bumping line bring-up and qualification for advanced packaging solutions including 2.5D/3DIC.

Qualifications

• Bachelor's degree or higher in a relevant engineering field with significant hands-on experience.
• Experience in silicon interconnect, bumping, or RDL process qualification and production.
• Proven ability to lead NPI and high-volume manufacturing ramp.

Responsibilities

• Define bumping process flows (passivation/UBM/RDL/bump) and establish process windows.
• Lead DOE-based optimization and engage suppliers to improve yield and reliability.
• Oversee bumping line bring-up, qualification, and production release for NPI/HVM.
• Collaborate with foundries, OSATs, and package design teams for robust solutions.
• Drive multi-source capacity expansion and continuous improvement programs.

Skills

Bumping process

Flip-chip design

DOE design & analysis

SPC & GR&R

RDL/2.5D/3DIC

Metrology & inline controls

Supplier management

Line bring-up & ramp

Capacity expansion

Packaging integration

Education

Bachelor's degree (Chemical/Electrical/Mechanical or related)

Master's degree (Chemical/Electrical/Mechanical or related)

PhD in Chemical/Electrical/Mechanical or related

Tools

Calibre

Virtuoso

CAD

SiP

GDS

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > Packaging Engineering

General Summary

The engineer will be a key member of the Process Package Integration and bumping process team, driving technology development and new product introduction (NPI) with primary ownership of wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness across multiple silicon technology nodes, foundries, bumping lines, and assembly houses (OSATs). Key responsibilities include defining bumping process flows (passivation/UBM/RDL/bump), establishing process windows and controls, leading DOE-based optimization, and partnering with suppliers to improve yield, reliability, and cost. The role works closely with foundry FBEOL teams, bumping/assembly partners, and internal package design, process, quality, test, and product development teams to deliver robust bumping solutions enabling advanced packaging (flip-chip, RDL/fan-out, and 2.5D/3DIC). The candidate will also lead bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness.

Skill/Knowledge

• Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL (as applicable), solder/Cu pillar bump formation, and associated materials/equipment.
• Deep knowledge of flip-chip bump design intent and assembly interactions (bump metallurgy, pitch scaling, coplanarity, warpage interactions), and wafer-level packaging (RDL) / fan-out process considerations impacting bumping.
• Strong technical skills in bumping process/material/equipment characterization (metrology and inline controls), failure analysis, DOE design, statistical data analysis, and FMEA to drive yield and reliability improvements.
• Experience leading bumping process qualification and production release activities (process window definition, control plans/SPC, GR&R, and risk mitigation) for NPI and high-volume manufacturing.
• Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies (2.5D/3DIC).
• Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp (HVM readiness).
• Hands‑on experience in project leadership and supplier management for external bumping houses/OSATs, including KPI definition, yield excursions containment, and continuous improvement programs.
• Experienced interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion.
• Understanding of heterogeneous integration (2.5D/3DIC) packaging flows and how bumping/interconnect schemes (micro‑bumps, fine-pitch RDL) impact downstream assembly and reliability.
• Ability to design and drive novel test vehicles/structures for bump/RDL process characterization and process-package interaction (reliability, electromigration, mechanical integrity).
• Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
• Understanding of chip-top physical design flow and communication with package design teams.
• Minimum of 8–10 years hands‑on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.

Additional Skills

• Good analytical and project management skills.
• Excellent capability of innovation and creativity.
• Highly motivated and committed to success of the individual and the team.
• Superior interpersonal communication skills. Publish technical reports.
• Able to work flexible hours. Occasional domestic/international travels needed.

Minimum Qualifications

• Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering or related work experience.
• Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.
• PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability‑[e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits

$191,800.00 - $287,800.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales‑incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.