IC Packaging FEA Engineer — Warpage, CPI & Reliability

Qualcomm; San Diego (CA); On-site; USD 154,000 - 231,000; Full time

Job summary

Qualcomm in San Diego seeks a Senior IC Packaging FEA Engineer to develop mechanical models (ANSYS APDL/Workbench) and perform warpage and reliability analyses for next‑generation package designs. You will build robust simulations that guide design and test correlation.

You will collaborate with design, NPI and CPI teams, characterize materials, develop BKMs, and drive test correlation while supporting manufacturing and reliability goals. Occasional travel may be required.

Qualifications

• Bachelor''s degree with 4+ years of System/Package Design/Technology Engineering experience.
• Master''s degree with 3+ years of System/Package Design/Technology Engineering experience.
• PhD with 2+ years of System/Package Design/Technology Engineering experience.
• PhD preferred with 6+ years in FEA for IC packaging; 3+ years ANSYS experience; 4+ years semiconductor packaging experience.

Responsibilities

• Warpage/Stress analysis
• Solder joint reliability (SJR) prediction
• Package assembly process simulation
• Chip-package interaction (CPI) analysis
• Use advanced FEA techniques (sub-modeling, contact, nonlinear analysis)
• Material characterization/testing and DOE planning

Skills

FEA expertise

Communication skills

Project execution

Education

Bachelor''s degree in relevant engineering fields

Master''s degree in engineering

PhD in engineering

Tools

ANSYS APDL

ANSYS Workbench

DOE

Job description

Qualcomm in San Diego seeks a Senior IC Packaging FEA Engineer to develop mechanical models (ANSYS APDL/Workbench) and perform warpage and reliability analyses for next‑generation package designs. You will build robust simulations that guide design and test correlation.

You will collaborate with design, NPI and CPI teams, characterize materials, develop BKMs, and drive test correlation while supporting manufacturing and reliability goals. Occasional travel may be required.