Packaging Engineer

Apple; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple in San Francisco seeks a senior IC packaging engineer to develop Custom Silicon packaging solutions in a module/system for consumer markets. You will interface between internal product design, quality, supply chain and external suppliers to develop and deploy new packaging technologies.

The role demands a BS with 10+ years, and a preference for MS/PhD with 10+ years in IC packaging, plus hands-on Wafer Level Packaging and reliability testing.

Qualifications

• BS and 10+ years of relevant industry experience.
• Preferred MS/PhD in mechanical engineering, physics, materials science or similar with 10+ years in IC packaging.
• Hands-on experience with Wafer Level Packaging and associated processes.

Responsibilities

• Interface between internal product design, quality, supply chain and external suppliers to develop and deploy new packaging technologies.
• Lead development to high-volume manufacturing and reduce cycle times.
• Present designs and data at team and executive reviews.

Skills

IC packaging

Wafer Level Packaging

Design of Experiments

Negotiation

Communication

Education

Bachelor's degree in a related field

Master's or PhD in a relevant field

Tools

AutoCAD

APD

Job description

Role Number: 200679730-3401

Summary

Looking for a senior level IC packaging engineer to develop exciting new products. You will be responsible providing Custom Silicon packaging solutions in a module/system for various consumer markets.

Description

• In this fast-paced environment, your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies.
• Must be a good negotiator and influencer to drive industry to meet company needs.
• We are looking for individuals who are very innovative with a proven track record to reduce package development cycle and qualify devices into a high-volume manufacturing environment.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.

Preferred Qualifications

• M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 10 years of experience in IC packaging. AutoCAD, APD and multi-physics simulation knowledge is a plus.
• Industry experience and work on WLP either in IDM or Fabless companies.
• Knowledge and hands-on experience on Wafer Bumping and Dielectric materials and their pros/cons is a must.
• Some hands-on knowledge in Manufacturing assembly processes; such as wafer back-grind, wafer dicing, Flip Chip die attach, encapsulation/molding, under-fill, ball attach, package singulation and Tape & Reel.
• In-depth knowledge in Wafer Level Chip Scale Packaging (RDL/Wafer Bumping & BEOL Assembly processes for Fan-In & Fan-Out designs).
• Good knowledge on Package Qualification and Reliability testing.
• Expert level knowledge of common reliability failure modes. Able to understand device physics and component/board level reliability testing.
• Proven track record to bring a product/package from conceptual stage to development and to HVM environment.
• Ability to construct Designs of Experiments and down-select materials and processes.
• Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at team meetings and executive review meetings.
• Able to perform independent research and development work with minimal supervision.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.