Senior Package SIPI Architect: 2.5D/3D IC Packaging

Astera Labs

San Jose, Northern (CA, KY)

Hybrid

USD 203,000 - 240,000

Full time

2 days ago

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Job summary

Astera Labs seeks a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products in San Jose, CA. You will drive packaging architecture across FCBGA, chiplet, and 2.5D/3D platforms, coordinating with silicon, PCB, and OSAT partners to ensure performance and manufacturability.

You will lead methodology, modeling, and correlation efforts, delivering robust SIPI signoffs while mentoring engineers and balancing cost,

Qualifications

10+ years in signal integrity, power integrity, or chip–package–board co-design.
Deep SIPI modeling, analysis, optimization, and signoff across high‑speed systems.
Experience with PCIe, CXL, Ethernet, and high‑speed SerDes design.
Proven track record delivering SIPI solutions for advanced packaging.

Responsibilities

Define SIPI architecture and design strategy for PCIe, CXL, Ethernet, and die‑to‑die interconnects.
Lead SI/PI simulations using HFSS, SIwave, Q3D to develop and sign off models.
Coordinate cross‑functional teams across silicon, package, PCB, and OSAT partners.
Drive simulation‑to‑measurement correlation with VNA, TDR, and high‑speed instruments.
Own SIPI signoff for 2.5D/3D packaging, chiplets, interposers, and UCIe interfaces.
Establish modeling standards, automation, and signoff methodologies; mentor engineers.