Principal SIPI Architect – 2.5D/3D Packaging & PCIe/CXL

Astera Labs; San Jose (CA); On-site; USD 203,000 - 230,000; Full time

Job summary

Astera Labs seeks a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products. You will lead SIPI strategy across PCIe, CXL, Ethernet, 200G/400G SerDes, and die‑to‑die interconnect, collaborating with silicon, packaging, PCB, and OSAT teams to balance performance, cost, and manufacturability.

You will drive modeling standards, data‑driven validation, and co‑design across chip–package–board, ensuring scalable

Qualifications

• 10+ years in signal integrity, power integrity, package electrical design, or chip–package–board co-design.
• Deep expertise in SIPI modeling for high-speed interfaces.
• Experience with PCIe 5.0/6.0, PAM4 SerDes channel design, and eye-diagram analysis.
• Proven track record delivering high-performance packages (FCBGA, 2.5D/3D, interposers).
• Hands-on with EM extraction and SIPI simulation tools.

Responsibilities

• Define SIPI architecture and design strategy for PCIe/CXL/Ethernet/SerDes interconnects.
• Perform SI/PI simulations using HFSS, SIwave, Q3D to develop and sign off models.
• Lead cross-functional execution across silicon, packaging, PCB, validation, and OSAT partners.
• Drive simulation-to-measurement correlation and lab validation (VNA, TDR, scope).
• Own SIPI simulation and signoff for 2.5D/3D platforms, including D2D interconnects (UCIe).
• Define routing guidelines for high-speed interfaces and impedance targets.
• Establish SIPI modeling standards, rules, and automation, mentoring teams.

Skills

Signal integrity

Power integrity

SIPI modeling

EM extraction

SI/PI sims

PCIe/CXL/SerDes

Package design

Vendor management

Co-design

2.5D/3D packaging

Tools

HFSS

SIwave

Q3D

3D Layout

Cadence Sigrity

Keysight ADS

Job description

Astera Labs seeks a Principal Package Signal & Power Integrity Engineer to architect, optimize, and sign off SIPI solutions for next‑gen connectivity products. You will lead SIPI strategy across PCIe, CXL, Ethernet, 200G/400G SerDes, and die‑to‑die interconnect, collaborating with silicon, packaging, PCB, and OSAT teams to balance performance, cost, and manufacturability.

You will drive modeling standards, data‑driven validation, and co‑design across chip–package–board, ensuring scalable