Senior Package Design Engineer - SoC, SiP & 3D Packaging

QUALCOMM, Inc.; San Diego (CA); On-site; USD 160,000 - 240,000; Full time

Benefits offered by this job

Annual bonus

RSU grants

Benefits package

Job summary

Qualcomm Technologies, Inc. is seeking an experienced Staff Package Design Engineer in San Diego to own advanced package selection and SI/PI optimization.

You will drive SoC packaging, work with multi-disciplinary teams to optimize mechanical, electrical, and thermal performance, and shape verification flows. The role requires a Master's in a related field with 5+ years of experience, familiarity with Cadence Allegro and various packaging configurations, and a strong background in high-speed

Qualifications

• Master's degree in electrical, mechanical, or materials science with 5+ years of experience
• Fundamentals in electrical, thermal, or mechanical engineering disciplines
• Familiarity with flip-chip BGA, 2.5D/3D interposer packaging configurations
• Experience with Cadence Allegro platform tools (APD/SiP, PCB Editor)
• Knowledge of high-speed interfaces (DDR, PCIe) and SI/PI considerations

Responsibilities

• Own and drive advanced package selection and generation of new generation product package structures
• Interface with multi-functional teams to optimize mechanical, electrical, and thermal performance
• Define and develop verification and automation strategies for package design flows
• Collaborate with BU PD teams to optimize floorplan and bump placement
• Explore new CAD tools and verification flows to improve design efficiency

Skills

Cadence APD/SiP

SiP xPD

Constraint Manager

Electrical/DFM/ERCE

High-speed signal integrity

Education

Master's degree in EE/ME/Materials

Tools

Cadence Allegro (PCB Editor, APD/SiP)

Xpedition (Siemens)

Calibre

XtractIM/PowerSI/HFSS/Q3D

Job description

Qualcomm Technologies, Inc. is seeking an experienced Staff Package Design Engineer in San Diego to own advanced package selection and SI/PI optimization.

You will drive SoC packaging, work with multi-disciplinary teams to optimize mechanical, electrical, and thermal performance, and shape verification flows. The role requires a Master's in a related field with 5+ years of experience, familiarity with Cadence Allegro and various packaging configurations, and a strong background in high-speed