Lead IC Packaging & SiP Design Engineer

Qualcomm Incorporated; San Diego (CA); On-site; USD 160,000 - 240,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an IC Package Design Engineer to drive advanced package selection and physical design of SoC packages.

You will optimize mechanical, electrical, and thermal performance, collaborate with multi-functional teams, and advance verification and automation strategies to streamline release flows. You will work with Cadence APD/SiP and Xpedition tools, ensure SI/PI compliance, and contribute to layout optimization and bump placement with the BU PD team across

Qualifications

• Experience with IC packaging structures and chip-package interactions.
• Knowledge of high-speed interfaces and PCB/packaging concepts.
• Experience with DRC/DFM/ER checks is preferred.

Responsibilities

• Own and drive advanced package selection and configuration optimization.
• Design and layout of packages; DV and tape-out.
• Coordinate with multi-functional teams for mechanical, electrical, and thermal optimization.
• Implement physical design of packages and modules for SoC.
• Develop verification and automation strategies to streamline design flows.
• Optimize chip floorplan and bump placement with BU PD team.

Skills

Cadence APD

SiP

Xpedition

Constraint Manager

DFM rules

ERC checks

Signal integrity

Package/SiP knowledge

Education

Master's degree in electrical engineering

Tools

Cadence Allegro

PCB Editor

APD/SiP

Job description

Qualcomm Technologies, Inc. is seeking an IC Package Design Engineer to drive advanced package selection and physical design of SoC packages.

You will optimize mechanical, electrical, and thermal performance, collaborate with multi-functional teams, and advance verification and automation strategies to streamline release flows. You will work with Cadence APD/SiP and Xpedition tools, ensure SI/PI compliance, and contribute to layout optimization and bump placement with the BU PD team across