Senior Package Design Engineer for High-Speed ASICs

Advanced Technology Search; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading recruitment firm is looking for a Package Design Engineer to take responsibility for complex flip-chip-BGA package designs in a collaborative environment focusing on high-speed SerDes, AI, and HPC applications. The ideal candidate will have significant experience in package design along with skills in Cadence tools. This full-time role is based in San Jose, California and offers a chance to work on cutting-edge semiconductor projects.

Qualifications

• 12+ years’ experience in flip-chip-BGA package design is required.
• Knowledge of package-level signal and power integrity is essential.
• Ability to collaborate across multiple time zones is necessary.

Responsibilities

• Overall design responsibility for ASIC package designs.
• Schedule, prioritize, & track work across multiple projects.
• Collaborate with engineering experts for design integrity.

Skills

Cadence SKILL experience

Package design knowledge

Signal integrity

Self-management

Education

BSEE or similar field

MSEE or similar field

Tools

Cadence APD (Allegro Package Designer)

Job description

A leading recruitment firm is looking for a Package Design Engineer to take responsibility for complex flip-chip-BGA package designs in a collaborative environment focusing on high-speed SerDes, AI, and HPC applications. The ideal candidate will have significant experience in package design along with skills in Cadence tools. This full-time role is based in San Jose, California and offers a chance to work on cutting-edge semiconductor projects.