Package Design Engineer

Advanced Technology Search; Fort Collins, San Jose (CO, CA); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading technology recruitment firm is seeking an experienced Package Design Engineer in Fort Collins, Colorado. This role involves designing complex flip-chip-BGA packages, particularly for ASICs in high-speed SerDes and RF communications. The ideal candidate has over 12 years of relevant experience and strong skills in Cadence tools, collaboration, and project management. This position offers a chance to innovate within a worldwide R&D team focused on developing cutting-edge technologies.

Qualifications

• 12+ years’ experience in flip-chip-BGA package design.
• Knowledge of package-level signal integrity and power integrity.
• Experience with high-speed SerDes.

Responsibilities

• Overall design responsibility for ASIC package designs.
• Track work across multiple projects.
• Collaborate with a worldwide R&D team.

Skills

Cadence SKILL for Allegro

Package design

Signal integrity

Power integrity

Thermal analysis

Education

BSEE or similar

MSEE or similar

Tools

Cadence APD

Job description

Our client is seeking an experienced Package Design Engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D D/A converters (ADC & DAC).

You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You’ll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and also automate design tasks using Cadence SKILL.

RESPONSIBILITIES

• Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
• 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest
• Package Design of critical structures for SerDes, ADC/DAC, DDR, etc.
• Schedule, prioritize, & track your work across 2+ projects simultaneously

EDUCATION/EXPERIENCE & REQUIREMENTS

• BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• MSEE or similar field and 10+ years’ experience in flip-chip-BGA package design, including high-speed SerDes
• Knowledge of package-level signal integrity and power integrity, to apply to package designs
• Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK.
• Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers