Memory Packaging Architect - Next-Gen AI & Datacenter

1000 Micron Technology, Inc.

Boise (ID)

On-site

USD 143,000 - 398,000

Full time

4 days ago

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Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Equity

Job summary

Micron Technology, Inc. is seeking a highly skilled engineer to shape the next generation of memory packaging, pathfinding and system architectures.

You will drive cross‑stack optimization across silicon, package, board, and system, partnering with customers to translate ideas into scalable products for datacenter to edge‑AI platforms. You will leverage deep expertise in memory timing, signaling, and packaging processes, collaborating with silicon and system teams to set long-term technology

Qualifications

Master’s degree in EE/CE/CS or equivalent required.
6+ years hands-on memory systems packaging, signaling, IO/PDN design experience required.
Deep understanding of memory timing, signaling and packaging tech with EDA tools.

Responsibilities

Define next-generation package pathfinding and system architectures for speed, bandwidth and power.
Lead cross-stack co-optimization across silicon, package, board and system.
Drive long-term packaging strategy and influence industry standards.
Collaborate with silicon, design teams and customers for disruptive edge-AI and datacenter solutions.
Interface with internal partners, customers, BUs and senior leaders.