Senior Modem SOC RTL Architect for Space Communications

Blue Origin; Texas; Híbrido; USD 230.000 - 323.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, vision insurance

Stock options

Paid time off

Descripción de la vacante

Blue Origin is seeking a Senior Modem SOC Design Engineer to lead RTL design for modem datapath and PHY blocks in the TeraWave SOC. You will define microarchitecture from system specs, implement signal processing hardware, and build the Arm compute subsystem, interfaces, and debug support.

This is a senior IC role contributing to production silicon. The position requires at least five years in digital ASIC/SOC RTL design, Verilog/SystemVerilog expertise, and experience with AXI/SRAM, CoreSight,

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum 5 years of digital ASIC/SOC RTL design experience.
• Proficient in Verilog or SystemVerilog for modem/PHY blocks.
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers.
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction.

Responsabilidades

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks.
• Define microarchitecture from satellite communication system specifications and performance requirements.
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction.
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration.
• Integrate debug subsystem components using Arm CoreSight architecture and trace infrastructure.
• Design general purpose IO subsystem logic and config register interfaces.
• Integrate subsystem and SOC level blocks including clock and reset architecture.
• Support synthesis, timing constraint development, and timing closure with physical design teams.

Conocimientos

Digital ASIC/SOC RTL design

Verilog/SystemVerilog

Modem/PHY RTL design

Arm compute subsystem

Signal processing hardware (filters/FF

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Herramientas

Verilog/SystemVerilog

AXI interconnect

SRAM controllers

Arm CoreSight

LPDDR6 memory interfaces

Gigabit Ethernet / 25G SerDes

Descripción del empleo

Blue Origin is seeking a Senior Modem SOC Design Engineer to lead RTL design for modem datapath and PHY blocks in the TeraWave SOC. You will define microarchitecture from system specs, implement signal processing hardware, and build the Arm compute subsystem, interfaces, and debug support.

This is a senior IC role contributing to production silicon. The position requires at least five years in digital ASIC/SOC RTL design, Verilog/SystemVerilog expertise, and experience with AXI/SRAM, CoreSight,