Senior Modem SoC RTL Architect

Blue Origin; Seattle (WA); On-site; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k) with company match

Paid time off

Stock options

Job summary

Blue Origin is seeking a Senior Modem SOC Design Engineer to own RTL design for modem datapath and PHY blocks within the ASIC SOC team, building out the Arm compute subsystem and IO infrastructure. You will drive microarchitecture from system specs through RTL to SOC integration, collaborating with architecture, verification, and physical design teams to deliver production silicon.

The role emphasizes design verification, timing closure, and SOC integration, with responsibilities spanning AXI

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• Minimum 5 years of experience in digital ASIC or SOC RTL design.
• Experience with RTL design in Verilog or System Verilog for modem or PHY blocks.
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers.
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction.

Responsibilities

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks
• Define microarchitecture from satellite communication system specifications and performance requirements
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration
• Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
• Design general purpose IO subsystem logic and associated configuration register interfaces
• Integrate subsystem and SOC level blocks including clock and reset architecture
• Support synthesis, timing constraint development, and timing closure with physical design teams

Skills

ASIC/SOC RTL design

Verilog/SystemVerilog

Arm compute subsystem

Signal processing hardware

RTL debugging

Education

Bachelor's degree in Electrical Engineering/Computer Engineering

Master's degree in Electrical Engineering/Computer Engineering

Tools

Arm CoreSight

Job description

Blue Origin is seeking a Senior Modem SOC Design Engineer to own RTL design for modem datapath and PHY blocks within the ASIC SOC team, building out the Arm compute subsystem and IO infrastructure. You will drive microarchitecture from system specs through RTL to SOC integration, collaborating with architecture, verification, and physical design teams to deliver production silicon.

The role emphasizes design verification, timing closure, and SOC integration, with responsibilities spanning AXI