Senior Modem SoC RTL Engineer for Space Communications

Blue Origin; Van Horn (TX); Presencial; USD 230.000 - 323.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Stock options

401(k) with company match

Paid time off

Education support

Descripción de la vacante

Blue Origin is seeking a Senior Modem SOC Design Engineer to own RTL design for the modem datapath and PHY blocks within the TeraWave SOC. You will define microarchitecture from system specs, implement signal processing hardware, and build the Arm compute subsystem with AXI interconnect and SRAM controller integration.

You will collaborate with architecture, verification, and physical design teams to deliver production silicon, supporting timing closure, IO subsystem design, and debug

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• Minimum 5 years of experience in digital ASIC or SOC RTL design.
• Experience with RTL design in Verilog or SystemVerilog for modem or PHY blocks.
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers.
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction.

Responsabilidades

• Design RTL in Verilog or SystemVerilog for modem datapath and PHY blocks.
• Define microarchitecture from satellite communication system specifications and performance requirements.
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction.
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration.
• Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure.
• Design general purpose IO subsystem logic and associated configuration register interfaces.
• Integrate subsystem and SOC level blocks including clock and reset architecture.
• Support synthesis, timing constraint development, and timing closure with physical design teams.

Conocimientos

RTL design in Verilog/SystemVerilog

Arm compute subsystem design

Digital ASIC/SoC RTL design

Signal processing hardware (filters/FF

Educación

Bachelor's degree in Electrical/Computer Engineering

Master's degree (preferred)

Herramientas

AXI interconnect

SRAM controllers

Descripción del empleo

Blue Origin is seeking a Senior Modem SOC Design Engineer to own RTL design for the modem datapath and PHY blocks within the TeraWave SOC. You will define microarchitecture from system specs, implement signal processing hardware, and build the Arm compute subsystem with AXI interconnect and SRAM controller integration.

You will collaborate with architecture, verification, and physical design teams to deliver production silicon, supporting timing closure, IO subsystem design, and debug