Senior Modem SoC Design Engineer – RTL/ARM

Blue Origin; Central (TX); On-site; USD 230,000 - 323,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Life insurance

401(k) with company match

Education Support Program

Stock options

Paid time off

Paid holidays

Job summary

Blue Origin is hiring a Senior Modem SOC Design Engineer to own RTL design for modem datapath and PHY blocks within the TeraWave satellite system. You will develop the Arm compute subsystem, AXI interconnect, and SRAM integration, collaborating with architecture, verification, and physical-design teams to deliver production silicon.

The role requires 5+ years in digital ASIC/SOC RTL design and hands-on experience with Verilog/SystemVerilog, ARM subsystems, and signal processing hardware.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field.
• Minimum 5 years of experience in digital ASIC or SOC RTL design.
• Experience with RTL design in Verilog or System Verilog for modem or PHY blocks.
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers.
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction.

Responsibilities

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks.
• Define microarchitecture from satellite communication system specifications and performance requirements.
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction.
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration.
• Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure.
• Design general purpose IO subsystem logic and associated configuration register interfaces.
• Integrate subsystem and SOC level blocks including clock and reset architecture.
• Support synthesis, timing constraint development, and timing closure with physical design teams.

Skills

Verilog

SystemVerilog

RTL design

Modem datapath

PHY blocks

Arm compute subsystem

AXI interconnect

SRAM controllers

Digital ASIC design

Timing closure

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Related technical field

Tools

Arm CoreSight

Job description

Blue Origin is hiring a Senior Modem SOC Design Engineer to own RTL design for modem datapath and PHY blocks within the TeraWave satellite system. You will develop the Arm compute subsystem, AXI interconnect, and SRAM integration, collaborating with architecture, verification, and physical-design teams to deliver production silicon.

The role requires 5+ years in digital ASIC/SOC RTL design and hands-on experience with Verilog/SystemVerilog, ARM subsystems, and signal processing hardware.