Senior Modem SOC Architect for High-Speed Space Connectivity

Blue Origin; Central (TX); On-site; USD 269,000 - 377,000; Full time

Benefits offered by this job

Stock options

Paid time off

Education support program

401(k) with company match

Job summary

Blue Origin is seeking a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team to lead RTL design for the TeraWave modem SOC and its subsystems. This individual-contributor role defines microarchitecture from system specs and drives integration across the modem PHY, Arm compute, debug, and IO infrastructure, aligning decisions from specification to production silicon.

You will collaborate with architecture, software, performance modeling, and FPGA prototyping teams, acting as the

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12+ years of experience in digital ASIC or SOC RTL design.
• Experience defining microarchitecture for modem or communication SOC blocks from system specifications.
• Experience with Arm compute subsystem design, AXI interconnect, and SRAM controllers.
• Experience with high‑speed memory interfaces and SOC‑level integration.
• Experience with debug subsystem design using Arm CoreSight components.
• Experience with synthesis, timing constraints, and timing closure support.

Responsibilities

• Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems.
• Define microarchitecture based on satellite communication system specifications and performance requirements.
• Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration.
• Integrate debug subsystem components using Arm CoreSight architecture and trace infrastructure.
• Drive subsystem and SOC-level integration, including clock, reset, and GPIO subsystems.
• Serve as the technical interface to the system architecture, SOC architecture, and software architecture teams.
• Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation.

Skills

RTL design

Verilog

SystemVerilog

Arm compute subsystem

AXI interconnect

SRAM controller integration

Arm CoreSight

SOC‑level integration

debug subsystem design

synthesis & timing closure

microarchitecture definition

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree preferred

Job description

Blue Origin is seeking a Principal Modem SOC Design Engineer on the ASIC Engineering SOC Team to lead RTL design for the TeraWave modem SOC and its subsystems. This individual-contributor role defines microarchitecture from system specs and drives integration across the modem PHY, Arm compute, debug, and IO infrastructure, aligning decisions from specification to production silicon.

You will collaborate with architecture, software, performance modeling, and FPGA prototyping teams, acting as the