Senior Modem SOC RTL Design Lead

Blue Origin; Seattle (WA); On-site; USD 269,000 - 377,000; Full time

Benefits offered by this job

Stock options

Health benefits

Paid time off

Job summary

Blue Origin is seeking a Principal Modem SOC Design Engineer to lead RTL design for the modem SOC and subsystems within the ASIC Engineering SOC Team. You will define microarchitecture from system specs and drive integration across the modem PHY, Arm compute, debug, and IO infrastructure.

As the technical interface among architecture teams, you will align decisions from specification through production silicon, collaborating with performance modeling and FPGA prototyping teams.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12+ years of experience in digital ASIC or SOC RTL design.
• Experience defining microarchitecture for modem or communication SOC blocks from system specifications.
• Experience with Arm compute subsystem design, including AXI interconnect and SRAM controllers.
• Experience with LPDDR4/5/6 or other high-speed memory interfaces.
• Experience with high-speed Gigabit Ethernet interface subsystems.
• Experience with SOC-level integration, including bus fabric, clock, and reset architecture.
• Experience with debug subsystem design using Arm CoreSight components.
• Experience with synthesis, timing constraint development, and timing closure support.

Responsibilities

• Lead RTL design in Verilog or System Verilog for the modem SOC and its subsystems.
• Define microarchitecture based on satellite communication system specifications and performance requirements.
• Develop Arm compute subsystem logic, including AXI interconnect and SRAM controller integration.
• Integrate debug subsystem components using Arm CoreSight architecture and trace infrastructure.
• Drive subsystem and SOC-level integration, including clock, reset, and GPIO subsystems.
• Serve as the technical interface to system, SOC, and software architecture teams.
• Collaborate with performance modeling and FPGA prototyping teams on design decisions and validation.

Skills

RTL design

Arm compute subsystem design

Synthesis and timing closure

Memory interfaces LPDDR4/5/6

Gigabit Ethernet interfaces

SOC integration

Verilog/SystemVerilog

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree (preferred)

Tools

Verilog

SystemVerilog

Arm CoreSight

AXI interconnect

SRAM controllers

Job description

Blue Origin is seeking a Principal Modem SOC Design Engineer to lead RTL design for the modem SOC and subsystems within the ASIC Engineering SOC Team. You will define microarchitecture from system specs and drive integration across the modem PHY, Arm compute, debug, and IO infrastructure.

As the technical interface among architecture teams, you will align decisions from specification through production silicon, collaborating with performance modeling and FPGA prototyping teams.