Senior Modem SOC Architect for Space Connectivity

Blue Origin; San Diego (CA); Presencial; USD 230.000 - 323.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, vision

401(k) with company match

Stock options

Paid time off

Descripción de la vacante

Blue Origin seeks a Senior Modem SOC Design Engineer to design RTL for modem datapath and PHY blocks on the ASIC Engineering SOC Team in California. You will own the Arm compute subsystem and help deliver production silicon.

You will work from system specs through microarchitecture, RTL, SOC integration, and timing closure, collaborating with architecture, verification, and physical design teams. This is an individual contributor role with no direct reports.

Formación

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 5 years of experience in digital ASIC or SOC RTL design
• Experience with RTL design in Verilog or SystemVerilog for modem or PHY blocks
• Experience with Arm compute subsystem design including AXI interconnect and SRAM controllers
• Experience implementing signal processing hardware such as filters, FFT, or forward error correction

Responsabilidades

• Design RTL in Verilog or System Verilog for modem datapath and PHY blocks
• Define microarchitecture from satellite communication system specifications and performance requirements
• Implement signal processing hardware including filters, FFT, equalizers, and forward error correction
• Develop Arm compute subsystem logic including AXI interconnect and SRAM controller integration
• Integrate debug subsystem components using Arm CoreSight architecture and associated trace infrastructure
• Design general purpose IO subsystem logic and associated configuration register interfaces
• Integrate subsystem and SOC level blocks including clock and reset architecture
• Support synthesis, timing constraint development, and timing closure with physical design teams

Descripción del empleo

Blue Origin seeks a Senior Modem SOC Design Engineer to design RTL for modem datapath and PHY blocks on the ASIC Engineering SOC Team in California. You will own the Arm compute subsystem and help deliver production silicon.

You will work from system specs through microarchitecture, RTL, SOC integration, and timing closure, collaborating with architecture, verification, and physical design teams. This is an individual contributor role with no direct reports.