Senior ML IP/SoC Design Engineer

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a Hardware Architect for silicon development in Mountain View. You will contribute to ML IPs for Google Silicon SoCs and define microarchitectures, data flows, and integration needs for subsystems.

Lead RTL activities, run functional and performance simulations, and support customers through schedules and bring-up. The role requires extensive RTL experience with Verilog/SystemVerilog, leadership of IP/SoC teams, and strong ASIC methodology.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• 4 years of experience in leading IP/SoC design teams.
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.

Responsibilities

• Contribute to Machine Learning IPs for Google Silicon SoCs.
• Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development.
• Drive RTL development, debug functional/performance simulations.
• Meet schedule commitments and provide strong support to customers.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Job description

Google is seeking a Hardware Architect for silicon development in Mountain View. You will contribute to ML IPs for Google Silicon SoCs and define microarchitectures, data flows, and integration needs for subsystems.

Lead RTL activities, run functional and performance simulations, and support customers through schedules and bring-up. The role requires extensive RTL experience with Verilog/SystemVerilog, leadership of IP/SoC teams, and strong ASIC methodology.