Senior Mixed-Signal Verification Engineer (PCIe/USB/MIPI)

Nutanix; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced design verification engineer to join our team in validating high-speed mixed- signal IPs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, sensors).

The role covers pre- and post-silicon verification with a focus on SystemVerilog/UVM testbench development and coverage closure. Candidates should have 4+ years of ASIC verification experience and proficiency with industry-standard simulators.

Qualifications

• Master's or PhD in Electrical Engineering, Computer Engineering, or related field.
• 4+ years of ASIC design verification, or related work experience.
• Knowledge of SystemVerilog/UVM HVL and verification methodology.

Responsibilities

• Define pre-silicon and post-silicon test plans based on design specs and standards.
• Architect and develop testbenches using SystemVerilog/UVM and analog/mixed-signal sim.
• Author assertions in SVA, develop test cases, and ensure coverage closure.
• Collaborate with digital/analog, modeling, and SoC teams for PHY verification and post-silicon validation.

Skills

SystemVerilog/UVM

HVL methodologies

VCS

Xcelium/NCsim

Modelsim/Questa

VCFormal

Jaspergold

Python

Perl

Low power verification

Formal verification

Gate level simulation

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical/Computer Engineering

PhD in related field (optional)

Tools

VCS

Xcelium/NCsim

Modelsim/Questa

VCFormal

Jaspergold

Job description

Qualcomm Technologies, Inc. is seeking an experienced design verification engineer to join our team in validating high-speed mixed- signal IPs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, sensors).

The role covers pre- and post-silicon verification with a focus on SystemVerilog/UVM testbench development and coverage closure. Candidates should have 4+ years of ASIC verification experience and proficiency with industry-standard simulators.