Senior SoC Design Verification Lead

Eximietas Design LLC; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Eximietas Design LLC seeks a Senior Design Verification Engineer with 3–10 years of hands-on SoC verification experience. You will lead verification efforts, develop test benches for high-speed interfaces (PCIe, Ethernet, MIPI), and implement UVM-based strategies.

Proficiency with VCS/Xsim and VIP integration is required, along with power-aware verification using UPF. The role involves mentoring engineers, collaborating with cross-functional teams, and ensuring thorough verification signoff and

Qualifications

• 3–10 years hands-on SoC design verification experience.
• Expertise in UVM and SystemVerilog.
• IP- and SoC-level verification projects with VIP integration.

Responsibilities

• Lead verification efforts and manage verification plans for complex projects.
• Develop and implement verification strategies, test plans, and test benches for high-speed SoCs.
• Perform gate-level simulations and power-aware verification using Xprop and UPF.
• Mentor junior verification engineers and guide the team.
• Ensure verification signoff criteria are met and documentation is thorough.

Skills

SystemVerilog

UVM

SoC verification

Gate-level simulations

Power-aware verification

C-SystemVerilog handshake

C test cases for boot-up verification

Shell scripting

Makefile

Perl

VCS

Xsim

Synopsys VIPs

Cadence VIPs

PCIe

Ethernet

CXL

MIPI

I2C/I3C/SPI/UART/GPIO/QSPI

HDL design verification

Education

Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, or a related field

Master’s degree in Computer Science, Electrical/Electronics Engineering, or a related field

PhD in Computer Science, Electrical/Electronics Engineering, or a related field

Tools

VCS

Xsim

Waveform Analyzers

Synopsys VIPs

Cadence VIPs

Xprop

UPF

Job description

Eximietas Design LLC seeks a Senior Design Verification Engineer with 3–10 years of hands-on SoC verification experience. You will lead verification efforts, develop test benches for high-speed interfaces (PCIe, Ethernet, MIPI), and implement UVM-based strategies.

Proficiency with VCS/Xsim and VIP integration is required, along with power-aware verification using UPF. The role involves mentoring engineers, collaborating with cross-functional teams, and ensuring thorough verification signoff and