Senior Mixed-Signal Verification Engineer for SoC IPs

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego is seeking an experienced design verification engineer to join the engineering group, focusing on high-speed mixed-signal IP verification for PCIe, USB, MIPI, CXL, and more.

You will contribute across the full verification lifecycle from concept to tape-out and post-silicon support. The role requires 6+ years of ASIC verification, strong SystemVerilog/UVM skills, and proficiency with industry-standard EDA tools.

Qualifications

• Bachelor, Master, or PhD in Electrical/Computer Engineering or related field.
• 6+ years ASIC design verification experience.
• HVL methodology experience with SystemVerilog/UVM.
• Experience with multiple ASIC simulation/formal tools.

Responsibilities

• Define pre-silicon and post-silicon test plans based on design specs.
• Architect and develop the testbench using SystemVerilog/UVM and mixed-signal techniques.
• Author assertions, develop coverage models, and debug to achieve coverage closure.
• Collaborate with digital/analog, modeling, and SoC teams for PHY verification.

Skills

SystemVerilog/UVM

Testbench development

Python

Perl

Education

Bachelor's degree

Master's degree

PhD

Tools

VCS

Xcel­l ium/NCsim

Modelsim/Questa

VCFormal

JasperGold

Job description

Qualcomm Technologies, Inc. in San Diego is seeking an experienced design verification engineer to join the engineering group, focusing on high-speed mixed-signal IP verification for PCIe, USB, MIPI, CXL, and more.

You will contribute across the full verification lifecycle from concept to tape-out and post-silicon support. The role requires 6+ years of ASIC verification, strong SystemVerilog/UVM skills, and proficiency with industry-standard EDA tools.