Senior Mixed-Signal Verification Engineer

Optimalsemi; United States; On-site; USD 90,000 - 140,000; Full time

Job summary

FTS Inc is seeking a seasoned verification engineer to support a team of design engineers in validating mixed-signal integrated circuits. You will develop test benches, run regression tests, and work with engineers to resolve bugs while maintaining thorough bug tracking and documentation.

Key tasks include creating verification plans from datasheets, applying stimuli, and upgrading tools and flows with the EDA team.

Qualifications

• Minimum 5+ years of directly related verification experience.
• Experience running simulations and characterizing variance in analog/mixed-signal blocks.
• Pre-silicon verification of mixed-signal products.
• Create verification plans from datasheets and engineer inputs.

Responsibilities

• Develop test benches for mixed-signal IC verification.
• Run regression tests and track results.
• Collaborate with design engineers to reproduce and fix bugs.
• Upgrade tools and flows with the EDA team.
• Review designs to guide verification architecture and features.
• Provide DV status updates to stakeholders.

Skills

5+ years experience

Verilog-AMS

Verilog-A

SystemVerilog

UVM

Python

Perl

Bug tracking

Regression testing

Tools

Cadence Virtuoso

Verilog-AMS

Specman

SystemVerilog

Job description

FTS Inc is seeking a seasoned verification engineer to support a team of design engineers in validating mixed-signal integrated circuits. You will develop test benches, run regression tests, and work with engineers to resolve bugs while maintaining thorough bug tracking and documentation.

Key tasks include creating verification plans from datasheets, applying stimuli, and upgrading tools and flows with the EDA team.