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Retym is seeking a seasoned Mixed-Signal Verification Engineer for a well-funded startup developing next-generation high-speed communication technologies. You will design and implement verification strategies for digital and analog blocks using UVM, SystemVerilog, and AMS-based modeling.
You will create behavioural models for analog blocks, run extensive simulations across unit, cluster and top levels, and collaborate closely with analog designers to ensure portable, reusable test benches and
Retym is seeking a seasoned Mixed-Signal Verification Engineer for a well-funded startup developing next-generation high-speed communication technologies. You will design and implement verification strategies for digital and analog blocks using UVM, SystemVerilog, and AMS-based modeling.
You will create behavioural models for analog blocks, run extensive simulations across unit, cluster and top levels, and collaborate closely with analog designers to ensure portable, reusable test benches and