Lead Mixed-Signal Verification Engineer (Tapeout)

Nexperia; Dallas (TX); Hybrid; USD 110,000 - 160,000; Full time

Benefits offered by this job

Health, dental, and vision insurance

Retirement plan with company match

Paid time off and holidays

Job summary

Nexperia's Integrated Circuit Solutions (ICS) Group seeks a highly motivated Mixed Signal Design Verification Engineer to validate analog and mixed-signal IC designs before tapeout. You will lead pre-Si verification, develop environments, and collaborate with design and systems teams to ensure silicon meets specs and is manufacturable.

The role requires strong Verilog/SystemVerilog/UVM experience, Cadence Virtuoso proficiency, scripting, and excellent communication.

Qualifications

• Strong verification background in analog and mixed-signal ICs.
• Experience with Verilog-AMS/SystemVerilog and UVM for automated regressions.
• Familiarity with Cadence Virtuoso and EDA tool flow.
• Excellent communication and leadership abilities.

Responsibilities

• Lead DV to drive pre-tapeout verification and quality tapeouts.
• Develop a detailed pre-Si verification plan and environments; implement regressions.
• Create mixed-signal behavioral models and drive coverage goals.
• Interface across systems, design, test, and silicon validation to ensure complete verification.
• Analyze simulations, identify root causes, and propose actionable fixes.
• Support post-silicon validation and silicon-to-measured performance correlation.

Skills

Verilog/SystemVerilog

UVM

Analog design

Mixed-signal design

Education

Bachelor’s, Master’s or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Unix shell

TCL

Python

Perl

SKILL scripting

Job description

Nexperia's Integrated Circuit Solutions (ICS) Group seeks a highly motivated Mixed Signal Design Verification Engineer to validate analog and mixed-signal IC designs before tapeout. You will lead pre-Si verification, develop environments, and collaborate with design and systems teams to ensure silicon meets specs and is manufacturable.

The role requires strong Verilog/SystemVerilog/UVM experience, Cadence Virtuoso proficiency, scripting, and excellent communication.