Senior Mixed-Signal Verification Engineer - Equity & Impact

Platform Recruitment; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

Platform Recruitment's client is seeking a Senior Mixed-Signal Verification Engineer to own verification of analog/mixed-signal subsystems at the heart of high-speed IO. You will shape sign-off decisions that determine what ships to tape-out, with a small elite team and meaningful equity.

Expect hands-on AMS modeling (Verilog-AMS, real-number modeling), SystemVerilog assertions, and self-checking testbenches.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 5+ years of analog/mixed-signal verification on complex SoCs or mixed-signal IP.
• Hands-on expertise with AMS modeling and verification: Verilog-AMS, real-number modeling, and analog-digital co-simulation flows.
• Proficiency in SystemVerilog with assertion-based verification and self-checking testbench architecture.
• Demonstrated ability to model analog blocks and validate against transistor-level references.

Responsibilities

• Own verification strategy and test plans for mixed-signal subsystems, block level through top-level integration.
• Define modeling approach and fidelity tiers (real-number model vs. Verilog-AMS vs. transistor-level co-sim) and the associated accuracy/runtime trade-offs.
• Build self-checking testbenches for analog/digital interactions — loop convergence, mode transitions, clock-domain crossings.
• Drive AMS co-simulation flows and define functional coverage targeting analog corner behavior.
• Debug and root-cause failures across the analog/digital boundary through to closure.
• Own block- and subsystem-level sign-off for tape-out, including coverage closure.

Skills

AMS modeling

Verilog-AMS

SystemVerilog

Assertion-based verification

Self-checking testbench

Debug skills

Education

BS/MS in Electrical Engineering

Tools

Verilog-AMS tooling

Python scripting

Job description

Platform Recruitment's client is seeking a Senior Mixed-Signal Verification Engineer to own verification of analog/mixed-signal subsystems at the heart of high-speed IO. You will shape sign-off decisions that determine what ships to tape-out, with a small elite team and meaningful equity.

Expect hands-on AMS modeling (Verilog-AMS, real-number modeling), SystemVerilog assertions, and self-checking testbenches.