Mixed-Signal Design Verification Manager -10286

Peyton Resource Group; Richardson (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Peyton Resource Group seeks a Senior Mixed-Signal Design Verification Manager to lead a team of verification engineers responsible for top-level verification of mixed-signal and power-management ICs.

You will drive verification strategy, automation, and cross-functional collaboration to deliver high-quality semiconductor products. 15+ years in analog/mixed-signal, leadership experience, and strong UVM expertise are required.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 15+ years in analog/mixed-signal design or verification.
• Experience managing a team or leading a functional group.
• Hands-on expertise in UVM and power-management systems.
• Strong problem-solving, debugging, and collaboration skills.
• Expertise in mixed-signal simulation and silicon debugging.
• Knowledge of top-down design methodology is preferred.

Responsibilities

• Lead and develop a verification team across experience levels.
• Define technical direction and verification strategies.
• Lead customer-focused verification for motor drivers and PMICs.
• Develop metric-driven verification plans from specs.
• Create constrained-random tests and automated checkers (UVM).
• Model top-level sims with RNM and Verilog-AMS.
• Collaborate with design/test teams to resolve issues.
• Improve verification workflows and automation.

Skills

Leadership

Mentoring

Problem-solving

Communication

Collaboration

Mentor team

Team development

Education

Bachelor’s degree in Electrical Engineering

Master’s degree preferred

Tools

UVM

Verilog-AMS

SPICE/Spectre

SystemVerilog

Python

Shell scripting

Job description

Senior Mixed-Signal Design Verification Manager

Experience Level: Management

Job Type: Regular

Travel: 10% or less, domestic or international

Role Summary

Lead and develop a team of verification engineers responsible for top-level design verification of mixed-signal and power-management integrated circuits (ICs). Drive verification strategy, technical excellence, automation, and collaboration across design and test teams to deliver high-quality, reliable semiconductor products.

Key Responsibilities

• Manage, mentor, and grow verification engineers across experience levels.
• Define technical direction and verification strategies.
• Lead customer-focused verification for motor drivers, power-loss protection, point-of-load, and battery-management ICs.
• Develop and execute metric-driven verification plans based on functional, performance, and test specifications.
• Create constrained-random tests and automated checkers using UVM.
• Develop accurate real-number models (RNM) and Verilog-AMS models for top-level simulations.
• Collaborate with design teams to debug and resolve verification issues.
• Partner with design and test teams to improve first-pass silicon testability.
• Improve verification methodologies using industry best practices.
• Automate verification workflows and repetitive tasks.

Required Qualifications

• Bachelor’s degree in Electrical Engineering or a related field, emphasizing mixed-signal design and verification.
• 15+ years of relevant experience, or equivalent advanced education and experience, in analog/mixed-signal design or verification of analog and power-management ICs.
• Experience managing a team or serving as a functional team lead.
• Hands-on expertise in UVM, analog and digital design fundamentals, and power-management systems.
• Strong problem-solving, debugging, communication, and collaboration skills.
• Expertise in mixed-signal simulation, including SPICE/Spectre, event-based simulators, co-simulation environments, simulation debugging, and silicon debugging.

Preferred Qualifications

• Master’s degree in Electrical Engineering or a related field.
• Experience with top-down design methodology.
• Proficiency in shell scripting or Python.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with GUI-based and command-line simulation workflows.
• Proficiency in SystemVerilog assertions and functional coverage.
• Understanding of AI integration into verification workflows.